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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17864 { 176, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #176 = ADD16rr_DB
17954 { 266, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x4400000b0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #266 = ADC16rr
17955 { 267, 3, 1, 0, 16, 0, 0x4c00000b1ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #267 = ADC16rr_REV
17994 { 306, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #306 = ADD16rr
17995 { 307, 3, 1, 0, 1, 0, 0xc00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #307 = ADD16rr_REV
18087 { 399, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #399 = AND16rr
18088 { 400, 3, 1, 0, 1, 0, 0x8c00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #400 = AND16rr_REV
18240 { 552, 3, 1, 0, 59, 0, 0x2ec00020b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #552 = BTC16rr
18252 { 564, 3, 1, 0, 59, 0, 0x2cc00020b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #564 = BTR16rr
18264 { 576, 3, 1, 0, 59, 0, 0x2ac00020b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #576 = BTS16rr
18744 { 1056, 3, 1, 0, 156, 0|(1ULL<<MCID::Commutable), 0x2bc00020b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #1056 = IMUL16rr
19605 { 1917, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x2400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #1917 = OR16rr
19606 { 1918, 3, 1, 0, 1, 0, 0x2c00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #1918 = OR16rr_REV
20242 { 2554, 3, 1, 0, 16, 0, 0x6400000b0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2554 = SBB16rr
20243 { 2555, 3, 1, 0, 16, 0, 0x6c00000b1ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2555 = SBB16rr_REV
20324 { 2636, 3, 1, 0, 1022, 0, 0x29400020b0ULL, ImplicitList90, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2636 = SHLD16rrCL
20364 { 2676, 3, 1, 0, 638, 0, 0x2b400020b0ULL, ImplicitList90, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2676 = SHRD16rrCL
20456 { 2768, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xa400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2768 = SUB16rr
20457 { 2769, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xac00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2769 = SUB16rr_REV
32882 { 15194, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0xc400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #15194 = XOR16rr
32883 { 15195, 3, 1, 0, 1, 0, 0xcc00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #15195 = XOR16rr_REV