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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17862 { 174, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = ADD16ri8_DB
17863 { 175, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #175 = ADD16ri_DB
17951 { 263, 3, 1, 0, 16, 0, 0x20400800baULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #263 = ADC16ri
17952 { 264, 3, 1, 0, 925, 0, 0x20c00200baULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #264 = ADC16ri8
17991 { 303, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400800b8ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #303 = ADD16ri
17992 { 304, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c00200b8ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #304 = ADD16ri8
18084 { 396, 3, 1, 0, 1, 0, 0x20400800bcULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #396 = AND16ri
18085 { 397, 3, 1, 0, 1, 0, 0x20c00200bcULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #397 = AND16ri8
18239 { 551, 3, 1, 0, 59, 0, 0x2e800220bfULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #551 = BTC16ri8
18251 { 563, 3, 1, 0, 59, 0, 0x2e800220beULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #563 = BTR16ri8
18263 { 575, 3, 1, 0, 59, 0, 0x2e800220bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #575 = BTS16ri8
19602 { 1914, 3, 1, 0, 1, 0, 0x20400800b9ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #1914 = OR16ri
19603 { 1915, 3, 1, 0, 1, 0, 0x20c00200b9ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #1915 = OR16ri8
20036 { 2348, 3, 1, 0, 1018, 0, 0x30400200baULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2348 = RCL16ri
20066 { 2378, 3, 1, 0, 1014, 0, 0x30400200bbULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2378 = RCR16ri
20137 { 2449, 3, 1, 0, 281, 0, 0x30400200b8ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2449 = ROL16ri
20161 { 2473, 3, 1, 0, 281, 0, 0x30400200b9ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2473 = ROR16ri
20211 { 2523, 3, 1, 0, 290, 0, 0x30400200bfULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2523 = SAR16ri
20239 { 2551, 3, 1, 0, 16, 0, 0x20400800bbULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2551 = SBB16ri
20240 { 2552, 3, 1, 0, 925, 0, 0x20c00200bbULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2552 = SBB16ri8
20303 { 2615, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x30400200bcULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2615 = SHL16ri
20343 { 2655, 3, 1, 0, 290, 0, 0x30400200bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2655 = SHR16ri
20453 { 2765, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400800bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2765 = SUB16ri
20454 { 2766, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c00200bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2766 = SUB16ri8
32879 { 15191, 3, 1, 0, 1, 0, 0x20400800beULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #15191 = XOR16ri
32880 { 15192, 3, 1, 0, 1, 0, 0x20c00200beULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #15192 = XOR16ri8