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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17691 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
17692 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
17693 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
17694 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
17706 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
17707 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
17911 { 223, 1, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #223 = SEH_PushFrame
17912 { 224, 1, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #224 = SEH_PushReg
17916 { 228, 1, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #228 = SEH_StackAlign
17917 { 229, 1, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #229 = SEH_StackAlloc
17940 { 252, 1, 0, 0, 644, 0, 0x3540020001ULL, ImplicitList10, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #252 = AAD8i8
17941 { 253, 1, 0, 0, 669, 0, 0x3500020001ULL, ImplicitList11, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #253 = AAM8i8
17947 { 259, 1, 0, 0, 926, 0, 0x540080081ULL, ImplicitList9, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #259 = ADC16i16
17956 { 268, 1, 0, 0, 926, 0, 0x5400c0101ULL, ImplicitList14, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #268 = ADC32i32
17965 { 277, 1, 0, 0, 926, 0, 0x540110001ULL, ImplicitList15, ImplicitList15, OperandInfo3, -1 ,nullptr }, // Inst #277 = ADC64i32
17974 { 286, 1, 0, 0, 926, 0, 0x500020001ULL, ImplicitList8, ImplicitList8, OperandInfo3, -1 ,nullptr }, // Inst #286 = ADC8i8
17987 { 299, 1, 0, 0, 1, 0, 0x140080081ULL, ImplicitList10, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #299 = ADD16i16
17996 { 308, 1, 0, 0, 1, 0, 0x1400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #308 = ADD32i32
18005 { 317, 1, 0, 0, 1, 0, 0x140110001ULL, ImplicitList16, ImplicitList15, OperandInfo3, -1 ,nullptr }, // Inst #317 = ADD64i32
18014 { 326, 1, 0, 0, 1, 0, 0x100020001ULL, ImplicitList11, ImplicitList8, OperandInfo3, -1 ,nullptr }, // Inst #326 = ADD8i8
18080 { 392, 1, 0, 0, 1, 0, 0x940080081ULL, ImplicitList10, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #392 = AND16i16
18089 { 401, 1, 0, 0, 1, 0, 0x9400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #401 = AND32i32
18098 { 410, 1, 0, 0, 1, 0, 0x940110001ULL, ImplicitList16, ImplicitList15, OperandInfo3, -1 ,nullptr }, // Inst #410 = AND64i32
18107 { 419, 1, 0, 0, 1, 0, 0x900020001ULL, ImplicitList11, ImplicitList8, OperandInfo3, -1 ,nullptr }, // Inst #419 = AND8i8
18375 { 687, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xf40080081ULL, ImplicitList10, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #687 = CMP16i16
18384 { 696, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xf400c0101ULL, ImplicitList7, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #696 = CMP32i32
18393 { 705, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xf40110001ULL, ImplicitList16, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #705 = CMP64i32
18402 { 714, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xf00020001ULL, ImplicitList11, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #714 = CMP8i8
18765 { 1077, 1, 0, 0, 694, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3940020081ULL, nullptr, ImplicitList10, OperandInfo3, -1 ,nullptr }, // Inst #1077 = IN16ri
18767 { 1079, 1, 0, 0, 694, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3940020101ULL, nullptr, ImplicitList7, OperandInfo3, -1 ,nullptr }, // Inst #1079 = IN32ri
18769 { 1081, 1, 0, 0, 694, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3900020001ULL, nullptr, ImplicitList11, OperandInfo3, -1 ,nullptr }, // Inst #1081 = IN8ri
18790 { 1102, 1, 0, 0, 698, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3340020001ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1102 = INT
18803 { 1115, 1, 0, 0, 596, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0xe00000ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1115 = IRET
19058 { 1370, 1, 0, 0, 797, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3280e80101ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1370 = LRETIL
19059 { 1371, 1, 0, 0, 797, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3280e90001ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1371 = LRETIQ
19060 { 1372, 1, 0, 0, 797, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3280e80081ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1372 = LRETIW
19598 { 1910, 1, 0, 0, 1, 0, 0x340080081ULL, ImplicitList10, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #1910 = OR16i16
19607 { 1919, 1, 0, 0, 1, 0, 0x3400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #1919 = OR32i32
19617 { 1929, 1, 0, 0, 1, 0, 0x340110001ULL, ImplicitList16, ImplicitList15, OperandInfo3, -1 ,nullptr }, // Inst #1929 = OR64i32
19626 { 1938, 1, 0, 0, 1, 0, 0x300020001ULL, ImplicitList11, ImplicitList8, OperandInfo3, -1 ,nullptr }, // Inst #1938 = OR8i8
19639 { 1951, 1, 0, 0, 689, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x39c0020081ULL, ImplicitList10, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1951 = OUT16ir
19641 { 1953, 1, 0, 0, 689, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x39c0020101ULL, ImplicitList7, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1953 = OUT32ir
19643 { 1955, 1, 0, 0, 689, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3980020001ULL, ImplicitList11, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1955 = OUT8ir
19995 { 2307, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a80020081ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2307 = PUSH16i8
19999 { 2311, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a80020101ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2311 = PUSH32i8
20003 { 2315, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a00100101ULL, ImplicitList74, ImplicitList74, OperandInfo3, -1 ,nullptr }, // Inst #2315 = PUSH64i32
20004 { 2316, 1, 0, 0, 841, 0|(1ULL<<MCID::MayStore), 0x1a80020101ULL, ImplicitList74, ImplicitList74, OperandInfo3, -1 ,nullptr }, // Inst #2316 = PUSH64i8
20027 { 2339, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a00080081ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2339 = PUSHi16
20028 { 2340, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a000c0101ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2340 = PUSHi32
20124 { 2436, 1, 0, 0, 693, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0xe00000ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2436 = RET
20125 { 2437, 1, 0, 0, 796, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x3080e80101ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2437 = RETIL
20126 { 2438, 1, 0, 0, 796, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x3080e80101ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2438 = RETIQ
20127 { 2439, 1, 0, 0, 796, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3080e80081ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2439 = RETIW
20235 { 2547, 1, 0, 0, 926, 0, 0x740080081ULL, ImplicitList9, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #2547 = SBB16i16
20244 { 2556, 1, 0, 0, 926, 0, 0x7400c0101ULL, ImplicitList14, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #2556 = SBB32i32
20253 { 2565, 1, 0, 0, 926, 0, 0x740110001ULL, ImplicitList15, ImplicitList15, OperandInfo3, -1 ,nullptr }, // Inst #2565 = SBB64i32
20262 { 2574, 1, 0, 0, 926, 0, 0x700020001ULL, ImplicitList8, ImplicitList8, OperandInfo3, -1 ,nullptr }, // Inst #2574 = SBB8i8
20449 { 2761, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xb40080081ULL, ImplicitList10, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #2761 = SUB16i16
20458 { 2770, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xb400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #2770 = SUB32i32
20467 { 2779, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xb40110001ULL, ImplicitList16, ImplicitList15, OperandInfo3, -1 ,nullptr }, // Inst #2779 = SUB64i32
20476 { 2788, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xb00020001ULL, ImplicitList11, ImplicitList8, OperandInfo3, -1 ,nullptr }, // Inst #2788 = SUB8i8
20565 { 2877, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x2a40080081ULL, ImplicitList10, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #2877 = TEST16i16
20570 { 2882, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x2a400c0101ULL, ImplicitList7, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #2882 = TEST32i32
20575 { 2887, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x2a40110001ULL, ImplicitList16, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #2887 = TEST64i32
20580 { 2892, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x2a00020001ULL, ImplicitList11, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #2892 = TEST8i8
32842 { 15154, 1, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3180020078ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #15154 = XABORT
32875 { 15187, 1, 0, 0, 1, 0, 0xd40080081ULL, ImplicitList10, ImplicitList9, OperandInfo3, -1 ,nullptr }, // Inst #15187 = XOR16i16
32884 { 15196, 1, 0, 0, 1, 0, 0xd400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #15196 = XOR32i32
32893 { 15205, 1, 0, 0, 1, 0, 0xd40110001ULL, ImplicitList16, ImplicitList15, OperandInfo3, -1 ,nullptr }, // Inst #15205 = XOR64i32
32902 { 15214, 1, 0, 0, 1, 0, 0xd00020001ULL, ImplicitList11, ImplicitList8, OperandInfo3, -1 ,nullptr }, // Inst #15214 = XOR8i8