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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc18141 { 453, 2, 1, 0, 1003, 0, 0xc06000a039ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #453 = BLCFILL64rr
18145 { 457, 2, 1, 0, 1003, 0, 0xc0a000a03eULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #457 = BLCI64rr
18149 { 461, 2, 1, 0, 1003, 0, 0xc06000a03dULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #461 = BLCIC64rr
18153 { 465, 2, 1, 0, 1003, 0, 0xc0a000a039ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #465 = BLCMSK64rr
18157 { 469, 2, 1, 0, 1003, 0, 0xc06000a03bULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #469 = BLCS64rr
18169 { 481, 2, 1, 0, 1003, 0, 0xc06000a03aULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #481 = BLSFILL64rr
18173 { 485, 2, 1, 0, 47, 0, 0xfcd000403bULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #485 = BLSI64rr
18177 { 489, 2, 1, 0, 1003, 0, 0xc06000a03eULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #489 = BLSIC64rr
18181 { 493, 2, 1, 0, 47, 0, 0xfcd000403aULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #493 = BLSMSK64rr
18185 { 497, 2, 1, 0, 47, 0, 0xfcd0004039ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #497 = BLSR64rr
18215 { 527, 2, 1, 0, 49, 0, 0x2f00012031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #527 = BSF64rr
18221 { 533, 2, 1, 0, 51, 0, 0x2f40012031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #533 = BSR64rr
18236 { 548, 2, 0, 0, 56, 0, 0x28c0012030ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #548 = BT64rr
18400 { 712, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xe40010030ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #712 = CMP64rr
18401 { 713, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xec0010031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #713 = CMP64rr_REV
18433 { 745, 2, 1, 0, 1047, 0, 0x2c40012030ULL, ImplicitList16, ImplicitList15, OperandInfo118, -1 ,nullptr }, // Inst #745 = CMPXCHG64rr
19092 { 1404, 2, 1, 0, 184, 0, 0x2f40013031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #1404 = LZCNT64rr
19380 { 1692, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x2240010030ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #1692 = MOV64rr
19381 { 1693, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x22c0010031ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #1693 = MOV64rr_REV
19888 { 2200, 2, 1, 0, 269, 0, 0x2e00013031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2200 = POPCNT64rr
20276 { 2588, 2, 1, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList74, ImplicitList97, OperandInfo118, -1 ,nullptr }, // Inst #2588 = SEG_ALLOCA_64
20546 { 2858, 2, 1, 0, 1003, 0, 0xc06000a03fULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2858 = T1MSKC64rr
20579 { 2891, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2140010030ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2891 = TEST64rr
20602 { 2914, 2, 1, 0, 321, 0, 0x2f00013031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2914 = TZCNT64rr
20606 { 2918, 2, 1, 0, 1003, 0, 0xc06000a03cULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2918 = TZMSK64rr
25820 { 8132, 2, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1e00002030ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #8132 = VMREAD64rr
25927 { 8239, 2, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1e40002031ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #8239 = VMWRITE64rr