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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc18140 { 452, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a029ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #452 = BLCFILL64rm
18144 { 456, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc0a000a02eULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #456 = BLCI64rm
18148 { 460, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02dULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #460 = BLCIC64rm
18152 { 464, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc0a000a029ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #464 = BLCMSK64rm
18156 { 468, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02bULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #468 = BLCS64rm
18168 { 480, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02aULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #480 = BLSFILL64rm
18172 { 484, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xfcd000402bULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #484 = BLSI64rm
18176 { 488, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02eULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #488 = BLSIC64rm
18180 { 492, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xfcd000402aULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #492 = BLSMSK64rm
18184 { 496, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xfcd0004029ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #496 = BLSR64rm
18214 { 526, 6, 1, 0, 48, 0|(1ULL<<MCID::MayLoad), 0x2f00012021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #526 = BSF64rm
18220 { 532, 6, 1, 0, 50, 0|(1ULL<<MCID::MayLoad), 0x2f40012021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #532 = BSR64rm
18399 { 711, 6, 0, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xec0010021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #711 = CMP64rm
18478 { 790, 6, 1, 0, 768, 0|(1ULL<<MCID::MayLoad), 0xb40013821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #790 = CVTSD2SI64rm_Int
18506 { 818, 6, 1, 0, 875, 0|(1ULL<<MCID::MayLoad), 0xb40013021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #818 = CVTSS2SI64rm_Int
18514 { 826, 6, 1, 0, 768, 0|(1ULL<<MCID::MayLoad), 0xb00013821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #826 = CVTTSD2SI64rm
18515 { 827, 6, 1, 0, 768, 0|(1ULL<<MCID::MayLoad), 0xb00013821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #827 = CVTTSD2SI64rm_Int
18522 { 834, 6, 1, 0, 659, 0|(1ULL<<MCID::MayLoad), 0xb00013021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #834 = CVTTSS2SI64rm
18523 { 835, 6, 1, 0, 659, 0|(1ULL<<MCID::MayLoad), 0xb00013021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #835 = CVTTSS2SI64rm_Int
18624 { 936, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005e21ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #936 = ENQCMD64
18627 { 939, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005621ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #939 = ENQCMDS64
18795 { 1107, 6, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2000004821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1107 = INVEPT64
18800 { 1112, 6, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2080004821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1112 = INVPCID64
18802 { 1114, 6, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2040004821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1114 = INVVPID64
18930 { 1242, 6, 1, 0, 886, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80012021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1242 = LAR64rm
18971 { 1283, 6, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2d00012021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1283 = LFS64rm
18977 { 1289, 6, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2d40012021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1289 = LGS64rm
19068 { 1380, 6, 1, 0, 886, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0xc0012021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1380 = LSL64rm
19072 { 1384, 6, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2c80012021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1384 = LSS64rm
19091 { 1403, 6, 1, 0, 183, 0|(1ULL<<MCID::MayLoad), 0x2f40013021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #1403 = LZCNT64rm
19379 { 1691, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x22c0010021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1691 = MOV64rm
19416 { 1728, 6, 1, 0, 833, 0|(1ULL<<MCID::MayLoad), 0x3c00014021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1728 = MOVBE64rm
19424 { 1736, 6, 0, 0, 134, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00004e21ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1736 = MOVDIR64B64
19497 { 1809, 6, 1, 0, 729, 0|(1ULL<<MCID::MayLoad), 0x2fc0012021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1809 = MOVSX64rm16
19498 { 1810, 6, 1, 0, 729, 0|(1ULL<<MCID::MayLoad), 0x18c0010021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1810 = MOVSX64rm32
19499 { 1811, 6, 1, 0, 729, 0|(1ULL<<MCID::MayLoad), 0x2f80012021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1811 = MOVSX64rm8
19522 { 1834, 6, 1, 0, 729, 0|(1ULL<<MCID::MayLoad), 0x2dc0012021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1834 = MOVZX64rm16
19523 { 1835, 6, 1, 0, 729, 0|(1ULL<<MCID::MayLoad), 0x2d80012021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1835 = MOVZX64rm8
19887 { 2199, 6, 1, 0, 268, 0|(1ULL<<MCID::MayLoad), 0x2e00013021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #2199 = POPCNT64rm
20545 { 2857, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02fULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #2857 = T1MSKC64rm
20601 { 2913, 6, 1, 0, 320, 0|(1ULL<<MCID::MayLoad), 0x2f00013021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #2913 = TZCNT64rm
20605 { 2917, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02cULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #2917 = TZMSK64rm
21817 { 4129, 6, 1, 0, 400, 0|(1ULL<<MCID::MayLoad), 0x1004b70003821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4129 = VCVTSD2SI64Zrm_Int
21820 { 4132, 6, 1, 0, 874, 0|(1ULL<<MCID::MayLoad), 0x4b50003821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4132 = VCVTSD2SI64rm_Int
21842 { 4154, 6, 1, 0, 400, 0|(1ULL<<MCID::MayLoad), 0x1005e70003821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4154 = VCVTSD2USI64Zrm_Int
21898 { 4210, 6, 1, 0, 401, 0|(1ULL<<MCID::MayLoad), 0x804b70003021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4210 = VCVTSS2SI64Zrm_Int
21901 { 4213, 6, 1, 0, 986, 0|(1ULL<<MCID::MayLoad), 0x4b50003021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4213 = VCVTSS2SI64rm_Int
21908 { 4220, 6, 1, 0, 1241, 0|(1ULL<<MCID::MayLoad), 0x805e70003021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4220 = VCVTSS2USI64Zrm_Int
22162 { 4474, 6, 1, 0, 400, 0|(1ULL<<MCID::MayLoad), 0x1004b30003821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4474 = VCVTTSD2SI64Zrm
22163 { 4475, 6, 1, 0, 400, 0|(1ULL<<MCID::MayLoad), 0x1004b30003821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4475 = VCVTTSD2SI64Zrm_Int
22167 { 4479, 6, 1, 0, 874, 0|(1ULL<<MCID::MayLoad), 0x4b10003821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4479 = VCVTTSD2SI64rm
22168 { 4480, 6, 1, 0, 876, 0|(1ULL<<MCID::MayLoad), 0x4b10003821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4480 = VCVTTSD2SI64rm_Int
22180 { 4492, 6, 1, 0, 400, 0|(1ULL<<MCID::MayLoad), 0x1005e30003821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4492 = VCVTTSD2USI64Zrm
22181 { 4493, 6, 1, 0, 400, 0|(1ULL<<MCID::MayLoad), 0x1005e30003821ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4493 = VCVTTSD2USI64Zrm_Int
22190 { 4502, 6, 1, 0, 401, 0|(1ULL<<MCID::MayLoad), 0x804b30003021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4502 = VCVTTSS2SI64Zrm
22191 { 4503, 6, 1, 0, 401, 0|(1ULL<<MCID::MayLoad), 0x804b30003021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4503 = VCVTTSS2SI64Zrm_Int
22195 { 4507, 6, 1, 0, 986, 0|(1ULL<<MCID::MayLoad), 0x4b10003021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4507 = VCVTTSS2SI64rm
22196 { 4508, 6, 1, 0, 986, 0|(1ULL<<MCID::MayLoad), 0x4b10003021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4508 = VCVTTSS2SI64rm_Int
22208 { 4520, 6, 1, 0, 1241, 0|(1ULL<<MCID::MayLoad), 0x805e30003021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4520 = VCVTTSS2USI64Zrm
22209 { 4521, 6, 1, 0, 1241, 0|(1ULL<<MCID::MayLoad), 0x805e30003021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #4521 = VCVTTSS2USI64Zrm_Int
25926 { 8238, 6, 1, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1e40002021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #8238 = VMWRITE64rm