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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc18139 { 451, 2, 1, 0, 1003, 0, 0x806000a039ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #451 = BLCFILL32rr
18143 { 455, 2, 1, 0, 1003, 0, 0x80a000a03eULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #455 = BLCI32rr
18147 { 459, 2, 1, 0, 1003, 0, 0x806000a03dULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #459 = BLCIC32rr
18151 { 463, 2, 1, 0, 1003, 0, 0x80a000a039ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #463 = BLCMSK32rr
18155 { 467, 2, 1, 0, 1003, 0, 0x806000a03bULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #467 = BLCS32rr
18167 { 479, 2, 1, 0, 1003, 0, 0x806000a03aULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #479 = BLSFILL32rr
18171 { 483, 2, 1, 0, 47, 0, 0xbcd000403bULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #483 = BLSI32rr
18175 { 487, 2, 1, 0, 1003, 0, 0x806000a03eULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #487 = BLSIC32rr
18179 { 491, 2, 1, 0, 47, 0, 0xbcd000403aULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #491 = BLSMSK32rr
18183 { 495, 2, 1, 0, 47, 0, 0xbcd0004039ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #495 = BLSR32rr
18213 { 525, 2, 1, 0, 49, 0, 0x2f00002131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #525 = BSF32rr
18219 { 531, 2, 1, 0, 51, 0, 0x2f40002131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #531 = BSR32rr
18232 { 544, 2, 0, 0, 56, 0, 0x28c0002130ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #544 = BT32rr
18391 { 703, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xe40000130ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #703 = CMP32rr
18392 { 704, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xec0000131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #704 = CMP32rr_REV
18431 { 743, 2, 1, 0, 1047, 0, 0x2c40002130ULL, ImplicitList7, ImplicitList14, OperandInfo116, -1 ,nullptr }, // Inst #743 = CMPXCHG32rr
18929 { 1241, 2, 1, 0, 885, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80002131ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1241 = LAR32rr
19067 { 1379, 2, 1, 0, 1001, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc0002131ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1379 = LSL32rr
19090 { 1402, 2, 1, 0, 184, 0, 0x2f40003131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #1402 = LZCNT32rr
19363 { 1675, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x2240000130ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1675 = MOV32rr
19364 { 1676, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveReg), 0x22c0000131ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1676 = MOV32rr_REV
19494 { 1806, 2, 1, 0, 1, 0, 0x18c0000131ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1806 = MOVSX32rr32
19886 { 2198, 2, 1, 0, 269, 0, 0x2e00003131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2198 = POPCNT32rr
20275 { 2587, 2, 1, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList73, ImplicitList96, OperandInfo116, -1 ,nullptr }, // Inst #2587 = SEG_ALLOCA_32
20544 { 2856, 2, 1, 0, 1003, 0, 0x806000a03fULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2856 = T1MSKC32rr
20574 { 2886, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2140000130ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2886 = TEST32rr
20600 { 2912, 2, 1, 0, 321, 0, 0x2f00003131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2912 = TZCNT32rr
20604 { 2916, 2, 1, 0, 1003, 0, 0x806000a03cULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2916 = TZMSK32rr
25818 { 8130, 2, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1e00002030ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #8130 = VMREAD32rr
25925 { 8237, 2, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1e40002031ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #8237 = VMWRITE32rr