reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/X86/X86GenAsmMatcher.inc

 9230   { 4546 /* movl */, X86::MOV32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
23738   { 4333 /* mov */, X86::MOV32rr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GR32, MCK_GR32 }, },

gen/lib/Target/X86/X86GenDAGISel.inc

18478 /* 37281*/        OPC_EmitNode1, TARGET_VAL(X86::MOV32rr), 0,
20737 /* 42068*/      OPC_EmitNode1, TARGET_VAL(X86::MOV32rr), 0,
55502 /*117653*/        OPC_EmitNode1, TARGET_VAL(X86::MOV32rr), 0,

gen/lib/Target/X86/X86GenGlobalISel.inc

11549       GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOV32rr,

gen/lib/Target/X86/X86GenSubtargetInfo.inc

23055   case X86::MOV32rr:
23231   case X86::MOV32rr:

lib/Target/X86/X86DomainReassignment.cpp

  661     createReplacer(X86::MOV32rr, X86::KMOVDkk);

lib/Target/X86/X86ExpandPseudo.cpp

  293             TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)

lib/Target/X86/X86FastISel.cpp

 1546     case MVT::i32: MovInst = X86::MOV32rr;     break;

lib/Target/X86/X86FixupBWInsts.cpp

  323       BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)

lib/Target/X86/X86FixupLEAs.cpp

  130   case X86::MOV32rr:
  136                 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r

lib/Target/X86/X86FrameLowering.cpp

 1137               TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
 1448     unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
 1706       unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
 2464     const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;

lib/Target/X86/X86ISelLowering.cpp

30100     BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)

lib/Target/X86/X86InstrFoldTables.cpp

  300   { X86::MOV32rr,             X86::MOV32mr,             TB_FOLDED_STORE },
  533   { X86::MOV32rr,              X86::MOV32rm,              0 },

lib/Target/X86/X86InstrInfo.cpp

 2975     Opc = X86::MOV32rr;

lib/Target/X86/X86SpeculativeLoadHardening.cpp

 1371   case X86::MOV32rr: