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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenDAGISel.inc39943 /* 83607*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
39945 /* 83614*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
39953 /* 83635*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
39958 /* 83653*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
39969 /* 83685*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
39974 /* 83703*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
39986 /* 83738*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
39992 /* 83760*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
55250 /*117106*/ OPC_MorphNodeTo2, TARGET_VAL(X86::MOV32r0), 0,
55255 /*117115*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
55263 /*117135*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
55272 /*117158*/ OPC_EmitNode2, TARGET_VAL(X86::MOV32r0), 0,
gen/lib/Target/X86/X86GenGlobalISel.inc10798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r0,
lib/Target/X86/X86FastISel.cpp 1439 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32r0),
1889 { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv
1890 { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem
1896 { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv
1897 { X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem
1903 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv
1904 { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem
1953 TII.get(X86::MOV32r0), Zero32);
3690 unsigned SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass);
lib/Target/X86/X86FixupSetCC.cpp 143 BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
lib/Target/X86/X86FlagsCopyLowering.cpp 979 BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOV32r0), ZeroReg);
lib/Target/X86/X86ISelDAGToDAG.cpp 4880 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
lib/Target/X86/X86ISelLowering.cpp30589 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
lib/Target/X86/X86InstrInfo.cpp 513 case X86::MOV32r0:
651 case X86::MOV32r0: Value = 0; break;
3678 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
4081 case X86::MOV32r0:
4881 if (MI.getOpcode() == X86::MOV32r0) {
lib/Target/X86/X86InstructionSelector.cpp 1582 {X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U}, // UDiv
1583 {X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U}, // URem
1591 {X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U}, // UDiv
1592 {X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U}, // URem
1600 {X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U}, // UDiv
1601 {X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U}, // URem
1653 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0),
lib/Target/X86/X86SpeculativeLoadHardening.cpp 481 auto ZeroI = BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV32r0),