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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc20133 { 2445, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000a8ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2445 = ROL16mCL
20136 { 2448, 2, 1, 0, 282, 0, 0x34c00000b8ULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2448 = ROL16rCL
20139 { 2451, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0000128ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2451 = ROL32mCL
20142 { 2454, 2, 1, 0, 282, 0, 0x34c0000138ULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2454 = ROL32rCL
20145 { 2457, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0010028ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2457 = ROL64mCL
20148 { 2460, 2, 1, 0, 282, 0, 0x34c0010038ULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2460 = ROL64rCL
20151 { 2463, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3480000028ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2463 = ROL8mCL
20154 { 2466, 2, 1, 0, 282, 0, 0x3480000038ULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2466 = ROL8rCL
20157 { 2469, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000a9ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2469 = ROR16mCL
20160 { 2472, 2, 1, 0, 282, 0, 0x34c00000b9ULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2472 = ROR16rCL
20163 { 2475, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0000129ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2475 = ROR32mCL
20166 { 2478, 2, 1, 0, 282, 0, 0x34c0000139ULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2478 = ROR32rCL
20169 { 2481, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0010029ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2481 = ROR64mCL
20172 { 2484, 2, 1, 0, 282, 0, 0x34c0010039ULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2484 = ROR64rCL
20175 { 2487, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3480000029ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2487 = ROR8mCL
20178 { 2490, 2, 1, 0, 282, 0, 0x3480000039ULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2490 = ROR8rCL
20207 { 2519, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000afULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2519 = SAR16mCL
20210 { 2522, 2, 1, 0, 301, 0, 0x34c00000bfULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2522 = SAR16rCL
20213 { 2525, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c000012fULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2525 = SAR32mCL
20216 { 2528, 2, 1, 0, 301, 0, 0x34c000013fULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2528 = SAR32rCL
20219 { 2531, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c001002fULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2531 = SAR64mCL
20222 { 2534, 2, 1, 0, 301, 0, 0x34c001003fULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2534 = SAR64rCL
20225 { 2537, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x348000002fULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2537 = SAR8mCL
20228 { 2540, 2, 1, 0, 301, 0, 0x348000003fULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2540 = SAR8rCL
20299 { 2611, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000acULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2611 = SHL16mCL
20302 { 2614, 2, 1, 0, 301, 0, 0x34c00000bcULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2614 = SHL16rCL
20305 { 2617, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c000012cULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2617 = SHL32mCL
20308 { 2620, 2, 1, 0, 301, 0, 0x34c000013cULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2620 = SHL32rCL
20311 { 2623, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c001002cULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2623 = SHL64mCL
20314 { 2626, 2, 1, 0, 301, 0, 0x34c001003cULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2626 = SHL64rCL
20317 { 2629, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x348000002cULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2629 = SHL8mCL
20320 { 2632, 2, 1, 0, 301, 0, 0x348000003cULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2632 = SHL8rCL
20322 { 2634, 6, 0, 0, 640, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x29400020a0ULL, ImplicitList90, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2634 = SHLD16mrCL
20324 { 2636, 3, 1, 0, 1022, 0, 0x29400020b0ULL, ImplicitList90, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2636 = SHLD16rrCL
20326 { 2638, 6, 0, 0, 957, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2940002120ULL, ImplicitList90, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2638 = SHLD32mrCL
20328 { 2640, 3, 1, 0, 956, 0, 0x2940002130ULL, ImplicitList90, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2640 = SHLD32rrCL
20330 { 2642, 6, 0, 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2940012020ULL, ImplicitList90, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2642 = SHLD64mrCL
20332 { 2644, 3, 1, 0, 647, 0, 0x2940012030ULL, ImplicitList90, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2644 = SHLD64rrCL
20339 { 2651, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000adULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2651 = SHR16mCL
20342 { 2654, 2, 1, 0, 301, 0, 0x34c00000bdULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2654 = SHR16rCL
20345 { 2657, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c000012dULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2657 = SHR32mCL
20348 { 2660, 2, 1, 0, 301, 0, 0x34c000013dULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2660 = SHR32rCL
20351 { 2663, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c001002dULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2663 = SHR64mCL
20354 { 2666, 2, 1, 0, 301, 0, 0x34c001003dULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2666 = SHR64rCL
20357 { 2669, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x348000002dULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2669 = SHR8mCL
20360 { 2672, 2, 1, 0, 301, 0, 0x348000003dULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2672 = SHR8rCL
20362 { 2674, 6, 0, 0, 640, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b400020a0ULL, ImplicitList90, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2674 = SHRD16mrCL
20364 { 2676, 3, 1, 0, 638, 0, 0x2b400020b0ULL, ImplicitList90, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2676 = SHRD16rrCL
20366 { 2678, 6, 0, 0, 957, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b40002120ULL, ImplicitList90, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2678 = SHRD32mrCL
20368 { 2680, 3, 1, 0, 956, 0, 0x2b40002130ULL, ImplicitList90, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2680 = SHRD32rrCL
20370 { 2682, 6, 0, 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b40012020ULL, ImplicitList90, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2682 = SHRD64mrCL
20372 { 2684, 3, 1, 0, 647, 0, 0x2b40012030ULL, ImplicitList90, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2684 = SHRD64rrCL