|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenInstrInfo.inc19872 { 2184, 1, 1, 0, 605, 0|(1ULL<<MCID::MayLoad), 0x1600000082ULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2184 = POP16r
19872 { 2184, 1, 1, 0, 605, 0|(1ULL<<MCID::MayLoad), 0x1600000082ULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2184 = POP16r
19873 { 2185, 5, 0, 0, 940, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c00000a8ULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2185 = POP16rmm
19873 { 2185, 5, 0, 0, 940, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c00000a8ULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2185 = POP16rmm
19874 { 2186, 1, 1, 0, 593, 0|(1ULL<<MCID::MayLoad), 0x23c00000b8ULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2186 = POP16rmr
19874 { 2186, 1, 1, 0, 593, 0|(1ULL<<MCID::MayLoad), 0x23c00000b8ULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2186 = POP16rmr
19875 { 2187, 1, 1, 0, 837, 0|(1ULL<<MCID::MayLoad), 0x1600000102ULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2187 = POP32r
19875 { 2187, 1, 1, 0, 837, 0|(1ULL<<MCID::MayLoad), 0x1600000102ULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2187 = POP32r
19876 { 2188, 5, 0, 0, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c0000128ULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2188 = POP32rmm
19876 { 2188, 5, 0, 0, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c0000128ULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2188 = POP32rmm
19877 { 2189, 1, 1, 0, 593, 0|(1ULL<<MCID::MayLoad), 0x23c0000138ULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2189 = POP32rmr
19877 { 2189, 1, 1, 0, 593, 0|(1ULL<<MCID::MayLoad), 0x23c0000138ULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2189 = POP32rmr
19881 { 2193, 0, 0, 0, 649, 0|(1ULL<<MCID::MayLoad), 0x1840000081ULL, ImplicitList73, ImplicitList75, nullptr, -1 ,nullptr }, // Inst #2193 = POPA16
19882 { 2194, 0, 0, 0, 649, 0|(1ULL<<MCID::MayLoad), 0x1840000101ULL, ImplicitList73, ImplicitList75, nullptr, -1 ,nullptr }, // Inst #2194 = POPA32
19893 { 2205, 0, 0, 0, 678, 0|(1ULL<<MCID::MayLoad), 0x2740000081ULL, ImplicitList73, ImplicitList76, nullptr, -1 ,nullptr }, // Inst #2205 = POPF16
19894 { 2206, 0, 0, 0, 674, 0|(1ULL<<MCID::MayLoad), 0x2740000101ULL, ImplicitList73, ImplicitList76, nullptr, -1 ,nullptr }, // Inst #2206 = POPF32
19995 { 2307, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a80020081ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2307 = PUSH16i8
19995 { 2307, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a80020081ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2307 = PUSH16i8
19996 { 2308, 1, 0, 0, 841, 0|(1ULL<<MCID::MayStore), 0x1400000082ULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2308 = PUSH16r
19996 { 2308, 1, 0, 0, 841, 0|(1ULL<<MCID::MayStore), 0x1400000082ULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2308 = PUSH16r
19997 { 2309, 5, 0, 0, 941, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc00000aeULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2309 = PUSH16rmm
19997 { 2309, 5, 0, 0, 941, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc00000aeULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2309 = PUSH16rmm
19998 { 2310, 1, 0, 0, 732, 0|(1ULL<<MCID::MayStore), 0x3fc00000beULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2310 = PUSH16rmr
19998 { 2310, 1, 0, 0, 732, 0|(1ULL<<MCID::MayStore), 0x3fc00000beULL, ImplicitList73, ImplicitList73, OperandInfo65, -1 ,nullptr }, // Inst #2310 = PUSH16rmr
19999 { 2311, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a80020101ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2311 = PUSH32i8
19999 { 2311, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a80020101ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2311 = PUSH32i8
20000 { 2312, 1, 0, 0, 841, 0|(1ULL<<MCID::MayStore), 0x1400000102ULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2312 = PUSH32r
20000 { 2312, 1, 0, 0, 841, 0|(1ULL<<MCID::MayStore), 0x1400000102ULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2312 = PUSH32r
20001 { 2313, 5, 0, 0, 941, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc000012eULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2313 = PUSH32rmm
20001 { 2313, 5, 0, 0, 941, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc000012eULL, ImplicitList73, ImplicitList73, OperandInfo91, -1 ,nullptr }, // Inst #2313 = PUSH32rmm
20002 { 2314, 1, 0, 0, 732, 0|(1ULL<<MCID::MayStore), 0x3fc000013eULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2314 = PUSH32rmr
20002 { 2314, 1, 0, 0, 732, 0|(1ULL<<MCID::MayStore), 0x3fc000013eULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2314 = PUSH32rmr
20008 { 2320, 0, 0, 0, 646, 0|(1ULL<<MCID::MayStore), 0x1800000081ULL, ImplicitList75, ImplicitList73, nullptr, -1 ,nullptr }, // Inst #2320 = PUSHA16
20009 { 2321, 0, 0, 0, 646, 0|(1ULL<<MCID::MayStore), 0x1800000101ULL, ImplicitList75, ImplicitList73, nullptr, -1 ,nullptr }, // Inst #2321 = PUSHA32
20016 { 2328, 0, 0, 0, 942, 0|(1ULL<<MCID::MayStore), 0x2700000081ULL, ImplicitList76, ImplicitList73, nullptr, -1 ,nullptr }, // Inst #2328 = PUSHF16
20017 { 2329, 0, 0, 0, 650, 0|(1ULL<<MCID::MayStore), 0x2700000101ULL, ImplicitList76, ImplicitList73, nullptr, -1 ,nullptr }, // Inst #2329 = PUSHF32
20027 { 2339, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a00080081ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2339 = PUSHi16
20027 { 2339, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a00080081ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2339 = PUSHi16
20028 { 2340, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a000c0101ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2340 = PUSHi32
20028 { 2340, 1, 0, 0, 594, 0|(1ULL<<MCID::MayStore), 0x1a000c0101ULL, ImplicitList73, ImplicitList73, OperandInfo3, -1 ,nullptr }, // Inst #2340 = PUSHi32
20085 { 2397, 1, 1, 0, 288, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2397 = RDFLAGS32
20085 { 2397, 1, 1, 0, 288, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList73, ImplicitList73, OperandInfo62, -1 ,nullptr }, // Inst #2397 = RDFLAGS32
20086 { 2398, 1, 1, 0, 288, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList74, ImplicitList73, OperandInfo64, -1 ,nullptr }, // Inst #2398 = RDFLAGS64
20275 { 2587, 2, 1, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList73, ImplicitList96, OperandInfo116, -1 ,nullptr }, // Inst #2587 = SEG_ALLOCA_32
32828 { 15140, 1, 0, 0, 8, 0, 0x0ULL, ImplicitList73, ImplicitList96, OperandInfo62, -1 ,nullptr }, // Inst #15140 = WIN_ALLOCA_32
32830 { 15142, 1, 0, 0, 288, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList73, ImplicitList76, OperandInfo62, -1 ,nullptr }, // Inst #15142 = WRFLAGS32