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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc17936 { 248, 0, 0, 0, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #248 = XABORT_DEF
17996 { 308, 1, 0, 0, 1, 0, 0x1400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #308 = ADD32i32
18089 { 401, 1, 0, 0, 1, 0, 0x9400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #401 = AND32i32
18295 { 607, 0, 0, 0, 714, 0, 0x2640000101ULL, ImplicitList7, ImplicitList21, nullptr, -1 ,nullptr }, // Inst #607 = CDQ
18296 { 608, 0, 0, 0, 627, 0, 0x2600010001ULL, ImplicitList7, ImplicitList16, nullptr, -1 ,nullptr }, // Inst #608 = CDQE
18313 { 625, 0, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000207cULL, ImplicitList7, nullptr, nullptr, -1 ,nullptr }, // Inst #625 = CLZERO32r
18384 { 696, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xf400c0101ULL, ImplicitList7, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #696 = CMP32i32
18430 { 742, 6, 0, 0, 662, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2c40002120ULL, ImplicitList7, ImplicitList14, OperandInfo79, -1 ,nullptr }, // Inst #742 = CMPXCHG32rm
18431 { 743, 2, 1, 0, 1047, 0, 0x2c40002130ULL, ImplicitList7, ImplicitList14, OperandInfo116, -1 ,nullptr }, // Inst #743 = CMPXCHG32rr
18531 { 843, 0, 0, 0, 627, 0, 0x2600000101ULL, ImplicitList10, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #843 = CWDE
18747 { 1059, 5, 0, 0, 158, 0|(1ULL<<MCID::MayLoad), 0x3dc000012dULL, ImplicitList7, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #1059 = IMUL32m
18748 { 1060, 1, 0, 0, 159, 0, 0x3dc000013dULL, ImplicitList7, ImplicitList29, OperandInfo62, -1 ,nullptr }, // Inst #1060 = IMUL32r
18767 { 1079, 1, 0, 0, 694, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3940020101ULL, nullptr, ImplicitList7, OperandInfo3, -1 ,nullptr }, // Inst #1079 = IN32ri
18768 { 1080, 0, 0, 0, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3b40000101ULL, ImplicitList41, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #1080 = IN32rr
18934 { 1246, 6, 0, 0, 1046, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2c41002120ULL, ImplicitList7, ImplicitList14, OperandInfo79, -1 ,nullptr }, // Inst #1246 = LCMPXCHG32
19348 { 1660, 2, 0, 0, 1, 0|(1ULL<<MCID::MayLoad), 0x2840080303ULL, nullptr, ImplicitList7, OperandInfo267, -1 ,nullptr }, // Inst #1660 = MOV32ao16
19349 { 1661, 2, 0, 0, 1, 0|(1ULL<<MCID::MayLoad), 0x28400c0503ULL, nullptr, ImplicitList7, OperandInfo267, -1 ,nullptr }, // Inst #1661 = MOV32ao32
19350 { 1662, 2, 0, 0, 1, 0|(1ULL<<MCID::MayLoad), 0x2840120703ULL, nullptr, ImplicitList7, OperandInfo267, -1 ,nullptr }, // Inst #1662 = MOV32ao64
19355 { 1667, 2, 0, 0, 1, 0|(1ULL<<MCID::MayStore), 0x28c0080303ULL, ImplicitList7, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1667 = MOV32o16a
19356 { 1668, 2, 0, 0, 1, 0|(1ULL<<MCID::MayStore), 0x28c00c0503ULL, ImplicitList7, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1668 = MOV32o32a
19357 { 1669, 2, 0, 0, 1, 0|(1ULL<<MCID::MayStore), 0x28c0120703ULL, ImplicitList7, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1669 = MOV32o64a
19530 { 1842, 5, 0, 0, 158, 0|(1ULL<<MCID::MayLoad), 0x3dc000012cULL, ImplicitList7, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #1842 = MUL32m
19531 { 1843, 1, 0, 0, 159, 0, 0x3dc000013cULL, ImplicitList7, ImplicitList29, OperandInfo62, -1 ,nullptr }, // Inst #1843 = MUL32r
19607 { 1919, 1, 0, 0, 1, 0, 0x3400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #1919 = OR32i32
19641 { 1953, 1, 0, 0, 689, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x39c0020101ULL, ImplicitList7, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1953 = OUT32ir
20389 { 2701, 0, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000205eULL, ImplicitList7, nullptr, nullptr, -1 ,nullptr }, // Inst #2701 = SKINIT
20458 { 2770, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xb400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #2770 = SUB32i32
20570 { 2882, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x2a400c0101ULL, ImplicitList7, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #2882 = TEST32i32
25254 { 7566, 0, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000205aULL, ImplicitList7, nullptr, nullptr, -1 ,nullptr }, // Inst #7566 = VMLOAD32
25822 { 8134, 0, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40002058ULL, ImplicitList7, nullptr, nullptr, -1 ,nullptr }, // Inst #8134 = VMRUN32
25824 { 8136, 0, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000205bULL, ImplicitList7, nullptr, nullptr, -1 ,nullptr }, // Inst #8136 = VMSAVE32
32853 { 15165, 1, 0, 0, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c00a00f8ULL, nullptr, ImplicitList7, OperandInfo129, -1 ,nullptr }, // Inst #15165 = XBEGIN_2
32854 { 15166, 1, 0, 0, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x31c00e0178ULL, nullptr, ImplicitList7, OperandInfo129, -1 ,nullptr }, // Inst #15166 = XBEGIN_4
32858 { 15170, 2, 1, 0, 578, 0, 0x2400000102ULL, ImplicitList7, ImplicitList7, OperandInfo71, -1 ,nullptr }, // Inst #15170 = XCHG32ar
32858 { 15170, 2, 1, 0, 578, 0, 0x2400000102ULL, ImplicitList7, ImplicitList7, OperandInfo71, -1 ,nullptr }, // Inst #15170 = XCHG32ar
32884 { 15196, 1, 0, 0, 1, 0, 0xd400c0101ULL, ImplicitList7, ImplicitList14, OperandInfo3, -1 ,nullptr }, // Inst #15196 = XOR32i32