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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc18310 { 622, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000302eULL, nullptr, ImplicitList23, OperandInfo91, -1 ,nullptr }, // Inst #622 = CLRSSBSY
18781 { 1093, 1, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000303dULL, ImplicitList23, ImplicitList23, OperandInfo62, -1 ,nullptr }, // Inst #1093 = INCSSPD
18781 { 1093, 1, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000303dULL, ImplicitList23, ImplicitList23, OperandInfo62, -1 ,nullptr }, // Inst #1093 = INCSSPD
18782 { 1094, 1, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8001303dULL, ImplicitList23, ImplicitList23, OperandInfo64, -1 ,nullptr }, // Inst #1094 = INCSSPQ
18782 { 1094, 1, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8001303dULL, ImplicitList23, ImplicitList23, OperandInfo64, -1 ,nullptr }, // Inst #1094 = INCSSPQ
20102 { 2414, 2, 1, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x780003039ULL, ImplicitList23, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #2414 = RDSSPD
20103 { 2415, 2, 1, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x780013039ULL, ImplicitList23, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2415 = RDSSPQ
20203 { 2515, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000302dULL, ImplicitList23, ImplicitList23, OperandInfo91, -1 ,nullptr }, // Inst #2515 = RSTORSSP
20203 { 2515, 5, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000302dULL, ImplicitList23, ImplicitList23, OperandInfo91, -1 ,nullptr }, // Inst #2515 = RSTORSSP
20234 { 2546, 0, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000306aULL, ImplicitList23, ImplicitList23, nullptr, -1 ,nullptr }, // Inst #2546 = SAVEPREVSSP
20234 { 2546, 0, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4000306aULL, ImplicitList23, ImplicitList23, nullptr, -1 ,nullptr }, // Inst #2546 = SAVEPREVSSP
20279 { 2591, 0, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40003068ULL, ImplicitList23, ImplicitList23, nullptr, -1 ,nullptr }, // Inst #2591 = SETSSBSY
20279 { 2591, 0, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40003068ULL, ImplicitList23, ImplicitList23, nullptr, -1 ,nullptr }, // Inst #2591 = SETSSBSY