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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenInstrInfo.inc18295 { 607, 0, 0, 0, 714, 0, 0x2640000101ULL, ImplicitList7, ImplicitList21, nullptr, -1 ,nullptr }, // Inst #607 = CDQ
18547 { 859, 5, 0, 0, 115, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc000012eULL, ImplicitList21, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #859 = DIV32m
18548 { 860, 1, 0, 0, 116, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc000013eULL, ImplicitList21, ImplicitList29, OperandInfo62, -1 ,nullptr }, // Inst #860 = DIV32r
18721 { 1033, 5, 0, 0, 146, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc000012fULL, ImplicitList21, ImplicitList29, OperandInfo91, -1 ,nullptr }, // Inst #1033 = IDIV32m
18722 { 1034, 1, 0, 0, 147, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3dc000013fULL, ImplicitList21, ImplicitList29, OperandInfo62, -1 ,nullptr }, // Inst #1034 = IDIV32r
19705 { 2017, 7, 0, 0, 247, 0|(1ULL<<MCID::MayLoad), 0x184c026821ULL, ImplicitList21, ImplicitList70, OperandInfo102, -1 ,nullptr }, // Inst #2017 = PCMPESTRIrm
19706 { 2018, 3, 0, 0, 248, 0, 0x184c026831ULL, ImplicitList21, ImplicitList70, OperandInfo103, -1 ,nullptr }, // Inst #2018 = PCMPESTRIrr
19707 { 2019, 7, 0, 0, 249, 0|(1ULL<<MCID::MayLoad), 0x180c026821ULL, ImplicitList21, ImplicitList71, OperandInfo102, -1 ,nullptr }, // Inst #2019 = PCMPESTRMrm
19708 { 2020, 3, 0, 0, 250, 0, 0x180c026831ULL, ImplicitList21, ImplicitList71, OperandInfo103, -1 ,nullptr }, // Inst #2020 = PCMPESTRMrr
20091 { 2403, 0, 0, 0, 692, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80002001ULL, ImplicitList46, ImplicitList21, nullptr, -1 ,nullptr }, // Inst #2403 = RDMSR
20094 { 2406, 0, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000206eULL, ImplicitList46, ImplicitList21, nullptr, -1 ,nullptr }, // Inst #2406 = RDPKRUr
20591 { 2903, 1, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000283eULL, ImplicitList21, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #2903 = TPAUSE
20630 { 2942, 1, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000383eULL, ImplicitList21, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #2942 = UMWAIT
26956 { 9268, 7, 0, 0, 247, 0|(1ULL<<MCID::MayLoad), 0x185c026821ULL, ImplicitList21, ImplicitList70, OperandInfo102, -1 ,nullptr }, // Inst #9268 = VPCMPESTRIrm
26957 { 9269, 3, 0, 0, 248, 0, 0x185c026831ULL, ImplicitList21, ImplicitList70, OperandInfo103, -1 ,nullptr }, // Inst #9269 = VPCMPESTRIrr
26958 { 9270, 7, 0, 0, 249, 0|(1ULL<<MCID::MayLoad), 0x181c026821ULL, ImplicitList21, ImplicitList71, OperandInfo102, -1 ,nullptr }, // Inst #9270 = VPCMPESTRMrm
26959 { 9271, 3, 0, 0, 250, 0, 0x181c026831ULL, ImplicitList21, ImplicitList71, OperandInfo103, -1 ,nullptr }, // Inst #9271 = VPCMPESTRMrr