|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenInstrInfo.inc17862 { 174, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = ADD16ri8_DB
17863 { 175, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #175 = ADD16ri_DB
17864 { 176, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #176 = ADD16rr_DB
17865 { 177, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #177 = ADD32ri8_DB
17866 { 178, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #178 = ADD32ri_DB
17867 { 179, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #179 = ADD32rr_DB
17868 { 180, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #180 = ADD64ri32_DB
17869 { 181, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #181 = ADD64ri8_DB
17870 { 182, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #182 = ADD64rr_DB
17871 { 183, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #183 = ADD8ri_DB
17872 { 184, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #184 = ADD8rr_DB
17900 { 212, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #212 = MOV32r0
17901 { 213, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #213 = MOV32r1
17902 { 214, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #214 = MOV32r_1
17918 { 230, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #230 = SETB_C16r
17918 { 230, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #230 = SETB_C16r
17919 { 231, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #231 = SETB_C32r
17919 { 231, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #231 = SETB_C32r
17920 { 232, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo64, -1 ,nullptr }, // Inst #232 = SETB_C64r
17920 { 232, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo64, -1 ,nullptr }, // Inst #232 = SETB_C64r
17921 { 233, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #233 = SETB_C8r
17921 { 233, 1, 1, 0, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #233 = SETB_C8r
17922 { 234, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #234 = SHLDROT32ri
17923 { 235, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #235 = SHLDROT64ri
17924 { 236, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #236 = SHRDROT32ri
17925 { 237, 3, 1, 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #237 = SHRDROT64ri
17937 { 249, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #249 = XOR32_FP
17938 { 250, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #250 = XOR64_FP
17948 { 260, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400800aaULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #260 = ADC16mi
17948 { 260, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400800aaULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #260 = ADC16mi
17949 { 261, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c00200aaULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #261 = ADC16mi8
17949 { 261, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c00200aaULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #261 = ADC16mi8
17950 { 262, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4400000a0ULL, ImplicitList1, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #262 = ADC16mr
17950 { 262, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4400000a0ULL, ImplicitList1, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #262 = ADC16mr
17951 { 263, 3, 1, 0, 16, 0, 0x20400800baULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #263 = ADC16ri
17951 { 263, 3, 1, 0, 16, 0, 0x20400800baULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #263 = ADC16ri
17952 { 264, 3, 1, 0, 925, 0, 0x20c00200baULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #264 = ADC16ri8
17952 { 264, 3, 1, 0, 925, 0, 0x20c00200baULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #264 = ADC16ri8
17953 { 265, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x4c00000a1ULL, ImplicitList1, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #265 = ADC16rm
17953 { 265, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x4c00000a1ULL, ImplicitList1, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #265 = ADC16rm
17954 { 266, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x4400000b0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #266 = ADC16rr
17954 { 266, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x4400000b0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #266 = ADC16rr
17955 { 267, 3, 1, 0, 16, 0, 0x4c00000b1ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #267 = ADC16rr_REV
17955 { 267, 3, 1, 0, 16, 0, 0x4c00000b1ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #267 = ADC16rr_REV
17957 { 269, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400c012aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #269 = ADC32mi
17957 { 269, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400c012aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #269 = ADC32mi
17958 { 270, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c002012aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #270 = ADC32mi8
17958 { 270, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c002012aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #270 = ADC32mi8
17959 { 271, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x440000120ULL, ImplicitList1, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #271 = ADC32mr
17959 { 271, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x440000120ULL, ImplicitList1, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #271 = ADC32mr
17960 { 272, 3, 1, 0, 16, 0, 0x20400c013aULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #272 = ADC32ri
17960 { 272, 3, 1, 0, 16, 0, 0x20400c013aULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #272 = ADC32ri
17961 { 273, 3, 1, 0, 925, 0, 0x20c002013aULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #273 = ADC32ri8
17961 { 273, 3, 1, 0, 925, 0, 0x20c002013aULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #273 = ADC32ri8
17962 { 274, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x4c0000121ULL, ImplicitList1, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #274 = ADC32rm
17962 { 274, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x4c0000121ULL, ImplicitList1, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #274 = ADC32rm
17963 { 275, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x440000130ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #275 = ADC32rr
17963 { 275, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x440000130ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #275 = ADC32rr
17964 { 276, 3, 1, 0, 16, 0, 0x4c0000131ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #276 = ADC32rr_REV
17964 { 276, 3, 1, 0, 16, 0, 0x4c0000131ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #276 = ADC32rr_REV
17966 { 278, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204011002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #278 = ADC64mi32
17966 { 278, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204011002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #278 = ADC64mi32
17967 { 279, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c003002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #279 = ADC64mi8
17967 { 279, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c003002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #279 = ADC64mi8
17968 { 280, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x440010020ULL, ImplicitList1, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #280 = ADC64mr
17968 { 280, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x440010020ULL, ImplicitList1, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #280 = ADC64mr
17969 { 281, 3, 1, 0, 1005, 0, 0x204011003aULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #281 = ADC64ri32
17969 { 281, 3, 1, 0, 1005, 0, 0x204011003aULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #281 = ADC64ri32
17970 { 282, 3, 1, 0, 925, 0, 0x20c003003aULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #282 = ADC64ri8
17970 { 282, 3, 1, 0, 925, 0, 0x20c003003aULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #282 = ADC64ri8
17971 { 283, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x4c0010021ULL, ImplicitList1, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #283 = ADC64rm
17971 { 283, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x4c0010021ULL, ImplicitList1, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #283 = ADC64rm
17972 { 284, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x440010030ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #284 = ADC64rr
17972 { 284, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x440010030ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #284 = ADC64rr
17973 { 285, 3, 1, 0, 16, 0, 0x4c0010031ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #285 = ADC64rr_REV
17973 { 285, 3, 1, 0, 16, 0, 0x4c0010031ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #285 = ADC64rr_REV
17975 { 287, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200002002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #287 = ADC8mi
17975 { 287, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200002002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #287 = ADC8mi
17976 { 288, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x208002002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #288 = ADC8mi8
17976 { 288, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x208002002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #288 = ADC8mi8
17977 { 289, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x400000020ULL, ImplicitList1, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #289 = ADC8mr
17977 { 289, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x400000020ULL, ImplicitList1, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #289 = ADC8mr
17978 { 290, 3, 1, 0, 16, 0, 0x200002003aULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #290 = ADC8ri
17978 { 290, 3, 1, 0, 16, 0, 0x200002003aULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #290 = ADC8ri
17979 { 291, 3, 1, 0, 16, 0, 0x208002003aULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #291 = ADC8ri8
17979 { 291, 3, 1, 0, 16, 0, 0x208002003aULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #291 = ADC8ri8
17980 { 292, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x480000021ULL, ImplicitList1, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #292 = ADC8rm
17980 { 292, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x480000021ULL, ImplicitList1, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #292 = ADC8rm
17981 { 293, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x400000030ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #293 = ADC8rr
17981 { 293, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x400000030ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #293 = ADC8rr
17982 { 294, 3, 1, 0, 16, 0, 0x480000031ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #294 = ADC8rr_REV
17982 { 294, 3, 1, 0, 16, 0, 0x480000031ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #294 = ADC8rr_REV
17983 { 295, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x3d80004821ULL, ImplicitList1, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #295 = ADCX32rm
17983 { 295, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x3d80004821ULL, ImplicitList1, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #295 = ADCX32rm
17984 { 296, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80004831ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #296 = ADCX32rr
17984 { 296, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80004831ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #296 = ADCX32rr
17985 { 297, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x3d80014821ULL, ImplicitList1, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #297 = ADCX64rm
17985 { 297, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x3d80014821ULL, ImplicitList1, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #297 = ADCX64rm
17986 { 298, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80014831ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #298 = ADCX64rr
17986 { 298, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80014831ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #298 = ADCX64rr
17988 { 300, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400800a8ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #300 = ADD16mi
17989 { 301, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c00200a8ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #301 = ADD16mi8
17990 { 302, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #302 = ADD16mr
17991 { 303, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400800b8ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #303 = ADD16ri
17992 { 304, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c00200b8ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #304 = ADD16ri8
17993 { 305, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0xc00000a1ULL, nullptr, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #305 = ADD16rm
17994 { 306, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #306 = ADD16rr
17995 { 307, 3, 1, 0, 1, 0, 0xc00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #307 = ADD16rr_REV
17997 { 309, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400c0128ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #309 = ADD32mi
17998 { 310, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c0020128ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #310 = ADD32mi8
17999 { 311, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x40000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #311 = ADD32mr
18000 { 312, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400c0138ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #312 = ADD32ri
18001 { 313, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c0020138ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #313 = ADD32ri8
18002 { 314, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0xc0000121ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #314 = ADD32rm
18003 { 315, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x40000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #315 = ADD32rr
18004 { 316, 3, 1, 0, 1, 0, 0xc0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #316 = ADD32rr_REV
18006 { 318, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2040110028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #318 = ADD64mi32
18007 { 319, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c0030028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #319 = ADD64mi8
18008 { 320, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x40010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #320 = ADD64mr
18009 { 321, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2040110038ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #321 = ADD64ri32
18010 { 322, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c0030038ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #322 = ADD64ri8
18011 { 323, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0xc0010021ULL, nullptr, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #323 = ADD64rm
18012 { 324, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x40010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #324 = ADD64rr
18013 { 325, 3, 1, 0, 1, 0, 0xc0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #325 = ADD64rr_REV
18015 { 327, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2000020028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #327 = ADD8mi
18016 { 328, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2080020028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #328 = ADD8mi8
18017 { 329, 6, 0, 0, 944, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #329 = ADD8mr
18018 { 330, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2000020038ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #330 = ADD8ri
18019 { 331, 3, 1, 0, 1, 0, 0x2080020038ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #331 = ADD8ri8
18020 { 332, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0x80000021ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #332 = ADD8rm
18021 { 333, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x30ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #333 = ADD8rr
18022 { 334, 3, 1, 0, 1, 0, 0x80000031ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #334 = ADD8rr_REV
18064 { 376, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x3d80005021ULL, ImplicitList1, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #376 = ADOX32rm
18064 { 376, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x3d80005021ULL, ImplicitList1, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #376 = ADOX32rm
18065 { 377, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80005031ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #377 = ADOX32rr
18065 { 377, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80005031ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #377 = ADOX32rr
18066 { 378, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x3d80015021ULL, ImplicitList1, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #378 = ADOX64rm
18066 { 378, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x3d80015021ULL, ImplicitList1, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #378 = ADOX64rm
18067 { 379, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80015031ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #379 = ADOX64rr
18067 { 379, 3, 1, 0, 16, 0|(1ULL<<MCID::Commutable), 0x3d80015031ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #379 = ADOX64rr
18081 { 393, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400800acULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #393 = AND16mi
18082 { 394, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c00200acULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #394 = AND16mi8
18083 { 395, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #395 = AND16mr
18084 { 396, 3, 1, 0, 1, 0, 0x20400800bcULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #396 = AND16ri
18085 { 397, 3, 1, 0, 1, 0, 0x20c00200bcULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #397 = AND16ri8
18086 { 398, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0x8c00000a1ULL, nullptr, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #398 = AND16rm
18087 { 399, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #399 = AND16rr
18088 { 400, 3, 1, 0, 1, 0, 0x8c00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #400 = AND16rr_REV
18090 { 402, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400c012cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #402 = AND32mi
18091 { 403, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c002012cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #403 = AND32mi8
18092 { 404, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x840000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #404 = AND32mr
18093 { 405, 3, 1, 0, 1, 0, 0x20400c013cULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #405 = AND32ri
18094 { 406, 3, 1, 0, 1, 0, 0x20c002013cULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #406 = AND32ri8
18095 { 407, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0x8c0000121ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #407 = AND32rm
18096 { 408, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x840000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #408 = AND32rr
18097 { 409, 3, 1, 0, 1, 0, 0x8c0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #409 = AND32rr_REV
18099 { 411, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204011002cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #411 = AND64mi32
18100 { 412, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c003002cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #412 = AND64mi8
18101 { 413, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x840010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #413 = AND64mr
18102 { 414, 3, 1, 0, 1, 0, 0x204011003cULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #414 = AND64ri32
18103 { 415, 3, 1, 0, 1, 0, 0x20c003003cULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #415 = AND64ri8
18104 { 416, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0x8c0010021ULL, nullptr, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #416 = AND64rm
18105 { 417, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x840010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #417 = AND64rr
18106 { 418, 3, 1, 0, 1, 0, 0x8c0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #418 = AND64rr_REV
18108 { 420, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200002002cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #420 = AND8mi
18109 { 421, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x208002002cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #421 = AND8mi8
18110 { 422, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x800000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #422 = AND8mr
18111 { 423, 3, 1, 0, 1, 0, 0x200002003cULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #423 = AND8ri
18112 { 424, 3, 1, 0, 1, 0, 0x208002003cULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #424 = AND8ri8
18113 { 425, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0x880000021ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #425 = AND8rm
18114 { 426, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x800000030ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #426 = AND8rr
18115 { 427, 3, 1, 0, 1, 0, 0x880000031ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #427 = AND8rr_REV
18116 { 428, 7, 1, 0, 832, 0|(1ULL<<MCID::MayLoad), 0xbc90004021ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr }, // Inst #428 = ANDN32rm
18117 { 429, 3, 1, 0, 818, 0, 0xbc90004031ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr }, // Inst #429 = ANDN32rr
18118 { 430, 7, 1, 0, 832, 0|(1ULL<<MCID::MayLoad), 0xfc90004021ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr }, // Inst #430 = ANDN64rm
18119 { 431, 3, 1, 0, 818, 0, 0xfc90004031ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr }, // Inst #431 = ANDN64rr
18130 { 442, 7, 1, 0, 38, 0|(1ULL<<MCID::MayLoad), 0x3dd0004022ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr }, // Inst #442 = BEXTR32rm
18131 { 443, 3, 1, 0, 39, 0, 0x3dd0004032ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr }, // Inst #443 = BEXTR32rr
18132 { 444, 7, 1, 0, 38, 0|(1ULL<<MCID::MayLoad), 0x7dd0004022ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #444 = BEXTR64rm
18133 { 445, 3, 1, 0, 39, 0, 0x7dd0004032ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr }, // Inst #445 = BEXTR64rr
18134 { 446, 7, 1, 0, 1011, 0|(1ULL<<MCID::MayLoad), 0x4200cc021ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #446 = BEXTRI32mi
18135 { 447, 3, 1, 0, 1010, 0, 0x4200cc031ULL, nullptr, ImplicitList1, OperandInfo112, -1 ,nullptr }, // Inst #447 = BEXTRI32ri
18136 { 448, 7, 1, 0, 1011, 0|(1ULL<<MCID::MayLoad), 0x442010c021ULL, nullptr, ImplicitList1, OperandInfo113, -1 ,nullptr }, // Inst #448 = BEXTRI64mi
18137 { 449, 3, 1, 0, 1010, 0, 0x442010c031ULL, nullptr, ImplicitList1, OperandInfo114, -1 ,nullptr }, // Inst #449 = BEXTRI64ri
18138 { 450, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a029ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #450 = BLCFILL32rm
18139 { 451, 2, 1, 0, 1003, 0, 0x806000a039ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #451 = BLCFILL32rr
18140 { 452, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a029ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #452 = BLCFILL64rm
18141 { 453, 2, 1, 0, 1003, 0, 0xc06000a039ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #453 = BLCFILL64rr
18142 { 454, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x80a000a02eULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #454 = BLCI32rm
18143 { 455, 2, 1, 0, 1003, 0, 0x80a000a03eULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #455 = BLCI32rr
18144 { 456, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc0a000a02eULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #456 = BLCI64rm
18145 { 457, 2, 1, 0, 1003, 0, 0xc0a000a03eULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #457 = BLCI64rr
18146 { 458, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02dULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #458 = BLCIC32rm
18147 { 459, 2, 1, 0, 1003, 0, 0x806000a03dULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #459 = BLCIC32rr
18148 { 460, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02dULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #460 = BLCIC64rm
18149 { 461, 2, 1, 0, 1003, 0, 0xc06000a03dULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #461 = BLCIC64rr
18150 { 462, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x80a000a029ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #462 = BLCMSK32rm
18151 { 463, 2, 1, 0, 1003, 0, 0x80a000a039ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #463 = BLCMSK32rr
18152 { 464, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc0a000a029ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #464 = BLCMSK64rm
18153 { 465, 2, 1, 0, 1003, 0, 0xc0a000a039ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #465 = BLCMSK64rr
18154 { 466, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02bULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #466 = BLCS32rm
18155 { 467, 2, 1, 0, 1003, 0, 0x806000a03bULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #467 = BLCS32rr
18156 { 468, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02bULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #468 = BLCS64rm
18157 { 469, 2, 1, 0, 1003, 0, 0xc06000a03bULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #469 = BLCS64rr
18166 { 478, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02aULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #478 = BLSFILL32rm
18167 { 479, 2, 1, 0, 1003, 0, 0x806000a03aULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #479 = BLSFILL32rr
18168 { 480, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02aULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #480 = BLSFILL64rm
18169 { 481, 2, 1, 0, 1003, 0, 0xc06000a03aULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #481 = BLSFILL64rr
18170 { 482, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xbcd000402bULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #482 = BLSI32rm
18171 { 483, 2, 1, 0, 47, 0, 0xbcd000403bULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #483 = BLSI32rr
18172 { 484, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xfcd000402bULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #484 = BLSI64rm
18173 { 485, 2, 1, 0, 47, 0, 0xfcd000403bULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #485 = BLSI64rr
18174 { 486, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02eULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #486 = BLSIC32rm
18175 { 487, 2, 1, 0, 1003, 0, 0x806000a03eULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #487 = BLSIC32rr
18176 { 488, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02eULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #488 = BLSIC64rm
18177 { 489, 2, 1, 0, 1003, 0, 0xc06000a03eULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #489 = BLSIC64rr
18178 { 490, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xbcd000402aULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #490 = BLSMSK32rm
18179 { 491, 2, 1, 0, 47, 0, 0xbcd000403aULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #491 = BLSMSK32rr
18180 { 492, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xfcd000402aULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #492 = BLSMSK64rm
18181 { 493, 2, 1, 0, 47, 0, 0xfcd000403aULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #493 = BLSMSK64rr
18182 { 494, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xbcd0004029ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #494 = BLSR32rm
18183 { 495, 2, 1, 0, 47, 0, 0xbcd0004039ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #495 = BLSR32rr
18184 { 496, 6, 1, 0, 46, 0|(1ULL<<MCID::MayLoad), 0xfcd0004029ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #496 = BLSR64rm
18185 { 497, 2, 1, 0, 47, 0, 0xfcd0004039ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #497 = BLSR64rr
18210 { 522, 6, 1, 0, 48, 0|(1ULL<<MCID::MayLoad), 0x2f000020a1ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #522 = BSF16rm
18211 { 523, 2, 1, 0, 49, 0, 0x2f000020b1ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #523 = BSF16rr
18212 { 524, 6, 1, 0, 48, 0|(1ULL<<MCID::MayLoad), 0x2f00002121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #524 = BSF32rm
18213 { 525, 2, 1, 0, 49, 0, 0x2f00002131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #525 = BSF32rr
18214 { 526, 6, 1, 0, 48, 0|(1ULL<<MCID::MayLoad), 0x2f00012021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #526 = BSF64rm
18215 { 527, 2, 1, 0, 49, 0, 0x2f00012031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #527 = BSF64rr
18216 { 528, 6, 1, 0, 50, 0|(1ULL<<MCID::MayLoad), 0x2f400020a1ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #528 = BSR16rm
18217 { 529, 2, 1, 0, 51, 0, 0x2f400020b1ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #529 = BSR16rr
18218 { 530, 6, 1, 0, 50, 0|(1ULL<<MCID::MayLoad), 0x2f40002121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #530 = BSR32rm
18219 { 531, 2, 1, 0, 51, 0, 0x2f40002131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #531 = BSR32rr
18220 { 532, 6, 1, 0, 50, 0|(1ULL<<MCID::MayLoad), 0x2f40012021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #532 = BSR64rm
18221 { 533, 2, 1, 0, 51, 0, 0x2f40012031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #533 = BSR64rr
18225 { 537, 6, 0, 0, 54, 0|(1ULL<<MCID::MayLoad), 0x2e800220acULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #537 = BT16mi8
18226 { 538, 6, 0, 0, 55, 0|(1ULL<<MCID::MayLoad), 0x28c00020a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #538 = BT16mr
18227 { 539, 2, 0, 0, 56, 0, 0x2e800220bcULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #539 = BT16ri8
18228 { 540, 2, 0, 0, 56, 0, 0x28c00020b0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #540 = BT16rr
18229 { 541, 6, 0, 0, 54, 0|(1ULL<<MCID::MayLoad), 0x2e8002212cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #541 = BT32mi8
18230 { 542, 6, 0, 0, 55, 0|(1ULL<<MCID::MayLoad), 0x28c0002120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #542 = BT32mr
18231 { 543, 2, 0, 0, 56, 0, 0x2e8002213cULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr }, // Inst #543 = BT32ri8
18232 { 544, 2, 0, 0, 56, 0, 0x28c0002130ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #544 = BT32rr
18233 { 545, 6, 0, 0, 54, 0|(1ULL<<MCID::MayLoad), 0x2e8003202cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #545 = BT64mi8
18234 { 546, 6, 0, 0, 55, 0|(1ULL<<MCID::MayLoad), 0x28c0012020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #546 = BT64mr
18235 { 547, 2, 0, 0, 56, 0, 0x2e8003203cULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr }, // Inst #547 = BT64ri8
18236 { 548, 2, 0, 0, 56, 0, 0x28c0012030ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #548 = BT64rr
18237 { 549, 6, 0, 0, 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2e800220afULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #549 = BTC16mi8
18238 { 550, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ec00020a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #550 = BTC16mr
18239 { 551, 3, 1, 0, 59, 0, 0x2e800220bfULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #551 = BTC16ri8
18240 { 552, 3, 1, 0, 59, 0, 0x2ec00020b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #552 = BTC16rr
18241 { 553, 6, 0, 0, 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2e8002212fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #553 = BTC32mi8
18242 { 554, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ec0002120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #554 = BTC32mr
18243 { 555, 3, 1, 0, 59, 0, 0x2e8002213fULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #555 = BTC32ri8
18244 { 556, 3, 1, 0, 59, 0, 0x2ec0002130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #556 = BTC32rr
18245 { 557, 6, 0, 0, 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2e8003202fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #557 = BTC64mi8
18246 { 558, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ec0012020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #558 = BTC64mr
18247 { 559, 3, 1, 0, 59, 0, 0x2e8003203fULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #559 = BTC64ri8
18248 { 560, 3, 1, 0, 59, 0, 0x2ec0012030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #560 = BTC64rr
18249 { 561, 6, 0, 0, 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2e800220aeULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #561 = BTR16mi8
18250 { 562, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2cc00020a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #562 = BTR16mr
18251 { 563, 3, 1, 0, 59, 0, 0x2e800220beULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #563 = BTR16ri8
18252 { 564, 3, 1, 0, 59, 0, 0x2cc00020b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #564 = BTR16rr
18253 { 565, 6, 0, 0, 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2e8002212eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #565 = BTR32mi8
18254 { 566, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2cc0002120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #566 = BTR32mr
18255 { 567, 3, 1, 0, 59, 0, 0x2e8002213eULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #567 = BTR32ri8
18256 { 568, 3, 1, 0, 59, 0, 0x2cc0002130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #568 = BTR32rr
18257 { 569, 6, 0, 0, 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2e8003202eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #569 = BTR64mi8
18258 { 570, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2cc0012020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #570 = BTR64mr
18259 { 571, 3, 1, 0, 59, 0, 0x2e8003203eULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #571 = BTR64ri8
18260 { 572, 3, 1, 0, 59, 0, 0x2cc0012030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #572 = BTR64rr
18261 { 573, 6, 0, 0, 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2e800220adULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #573 = BTS16mi8
18262 { 574, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ac00020a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #574 = BTS16mr
18263 { 575, 3, 1, 0, 59, 0, 0x2e800220bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #575 = BTS16ri8
18264 { 576, 3, 1, 0, 59, 0, 0x2ac00020b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #576 = BTS16rr
18265 { 577, 6, 0, 0, 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2e8002212dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #577 = BTS32mi8
18266 { 578, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ac0002120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #578 = BTS32mr
18267 { 579, 3, 1, 0, 59, 0, 0x2e8002213dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #579 = BTS32ri8
18268 { 580, 3, 1, 0, 59, 0, 0x2ac0002130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #580 = BTS32rr
18269 { 581, 6, 0, 0, 57, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2e8003202dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #581 = BTS64mi8
18270 { 582, 6, 0, 0, 58, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ac0012020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #582 = BTS64mr
18271 { 583, 3, 1, 0, 59, 0, 0x2e8003203dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #583 = BTS64ri8
18272 { 584, 3, 1, 0, 59, 0, 0x2ac0012030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #584 = BTS64rr
18273 { 585, 7, 1, 0, 60, 0|(1ULL<<MCID::MayLoad), 0x3d50004022ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr }, // Inst #585 = BZHI32rm
18274 { 586, 3, 1, 0, 61, 0, 0x3d50004032ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr }, // Inst #586 = BZHI32rr
18275 { 587, 7, 1, 0, 60, 0|(1ULL<<MCID::MayLoad), 0x7d50004022ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #587 = BZHI64rm
18276 { 588, 3, 1, 0, 61, 0, 0x7d50004032ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr }, // Inst #588 = BZHI64rr
18301 { 613, 0, 0, 0, 1057, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000204aULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #613 = CLAC
18302 { 614, 0, 0, 0, 783, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #614 = CLC
18302 { 614, 0, 0, 0, 783, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #614 = CLC
18309 { 621, 0, 0, 0, 733, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e80000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #621 = CLI
18309 { 621, 0, 0, 0, 733, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e80000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #621 = CLI
18315 { 627, 0, 0, 0, 821, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3d40000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #627 = CMC
18315 { 627, 0, 0, 0, 821, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3d40000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #627 = CMC
18316 { 628, 8, 1, 0, 792, 0|(1ULL<<MCID::MayLoad), 0x10000020a4ULL, ImplicitList1, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #628 = CMOV16rm
18317 { 629, 4, 1, 0, 791, 0|(1ULL<<MCID::Commutable), 0x10000020b4ULL, ImplicitList1, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #629 = CMOV16rr
18318 { 630, 8, 1, 0, 792, 0|(1ULL<<MCID::MayLoad), 0x1000002124ULL, ImplicitList1, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #630 = CMOV32rm
18319 { 631, 4, 1, 0, 791, 0|(1ULL<<MCID::Commutable), 0x1000002134ULL, ImplicitList1, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #631 = CMOV32rr
18320 { 632, 8, 1, 0, 792, 0|(1ULL<<MCID::MayLoad), 0x1000012024ULL, ImplicitList1, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #632 = CMOV64rm
18321 { 633, 4, 1, 0, 791, 0|(1ULL<<MCID::Commutable), 0x1000012034ULL, ImplicitList1, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #633 = CMOV64rr
18323 { 635, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo137, -1 ,nullptr }, // Inst #635 = CMOVBE_Fp32
18324 { 636, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo138, -1 ,nullptr }, // Inst #636 = CMOVBE_Fp64
18325 { 637, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo139, -1 ,nullptr }, // Inst #637 = CMOVBE_Fp80
18327 { 639, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo137, -1 ,nullptr }, // Inst #639 = CMOVB_Fp32
18328 { 640, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo138, -1 ,nullptr }, // Inst #640 = CMOVB_Fp64
18329 { 641, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo139, -1 ,nullptr }, // Inst #641 = CMOVB_Fp80
18331 { 643, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo137, -1 ,nullptr }, // Inst #643 = CMOVE_Fp32
18332 { 644, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo138, -1 ,nullptr }, // Inst #644 = CMOVE_Fp64
18333 { 645, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo139, -1 ,nullptr }, // Inst #645 = CMOVE_Fp80
18335 { 647, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo137, -1 ,nullptr }, // Inst #647 = CMOVNBE_Fp32
18336 { 648, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo138, -1 ,nullptr }, // Inst #648 = CMOVNBE_Fp64
18337 { 649, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo139, -1 ,nullptr }, // Inst #649 = CMOVNBE_Fp80
18339 { 651, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo137, -1 ,nullptr }, // Inst #651 = CMOVNB_Fp32
18340 { 652, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo138, -1 ,nullptr }, // Inst #652 = CMOVNB_Fp64
18341 { 653, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo139, -1 ,nullptr }, // Inst #653 = CMOVNB_Fp80
18343 { 655, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo137, -1 ,nullptr }, // Inst #655 = CMOVNE_Fp32
18344 { 656, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo138, -1 ,nullptr }, // Inst #656 = CMOVNE_Fp64
18345 { 657, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo139, -1 ,nullptr }, // Inst #657 = CMOVNE_Fp80
18347 { 659, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo137, -1 ,nullptr }, // Inst #659 = CMOVNP_Fp32
18348 { 660, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo138, -1 ,nullptr }, // Inst #660 = CMOVNP_Fp64
18349 { 661, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo139, -1 ,nullptr }, // Inst #661 = CMOVNP_Fp80
18351 { 663, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo137, -1 ,nullptr }, // Inst #663 = CMOVP_Fp32
18352 { 664, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo138, -1 ,nullptr }, // Inst #664 = CMOVP_Fp64
18353 { 665, 3, 1, 0, 65, 0, 0xc00000ULL, ImplicitList1, ImplicitList13, OperandInfo139, -1 ,nullptr }, // Inst #665 = CMOVP_Fp80
18354 { 666, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #666 = CMOV_FR32
18355 { 667, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #667 = CMOV_FR32X
18356 { 668, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #668 = CMOV_FR64
18357 { 669, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #669 = CMOV_FR64X
18358 { 670, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #670 = CMOV_GR16
18359 { 671, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #671 = CMOV_GR32
18360 { 672, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #672 = CMOV_GR8
18361 { 673, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #673 = CMOV_RFP32
18362 { 674, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #674 = CMOV_RFP64
18363 { 675, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #675 = CMOV_RFP80
18364 { 676, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #676 = CMOV_VK16
18365 { 677, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #677 = CMOV_VK2
18366 { 678, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #678 = CMOV_VK32
18367 { 679, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #679 = CMOV_VK4
18368 { 680, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #680 = CMOV_VK64
18369 { 681, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #681 = CMOV_VK8
18370 { 682, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #682 = CMOV_VR128
18371 { 683, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #683 = CMOV_VR128X
18372 { 684, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #684 = CMOV_VR256
18373 { 685, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #685 = CMOV_VR256X
18374 { 686, 4, 1, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #686 = CMOV_VR512
18375 { 687, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xf40080081ULL, ImplicitList10, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #687 = CMP16i16
18376 { 688, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x20400800afULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #688 = CMP16mi
18377 { 689, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x20c00200afULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #689 = CMP16mi8
18378 { 690, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xe400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #690 = CMP16mr
18379 { 691, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x20400800bfULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #691 = CMP16ri
18380 { 692, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x20c00200bfULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #692 = CMP16ri8
18381 { 693, 6, 0, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xec00000a1ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #693 = CMP16rm
18382 { 694, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xe400000b0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #694 = CMP16rr
18383 { 695, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xec00000b1ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #695 = CMP16rr_REV
18384 { 696, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xf400c0101ULL, ImplicitList7, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #696 = CMP32i32
18385 { 697, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x20400c012fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #697 = CMP32mi
18386 { 698, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x20c002012fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #698 = CMP32mi8
18387 { 699, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xe40000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #699 = CMP32mr
18388 { 700, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x20400c013fULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr }, // Inst #700 = CMP32ri
18389 { 701, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x20c002013fULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr }, // Inst #701 = CMP32ri8
18390 { 702, 6, 0, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xec0000121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #702 = CMP32rm
18391 { 703, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xe40000130ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #703 = CMP32rr
18392 { 704, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xec0000131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #704 = CMP32rr_REV
18393 { 705, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xf40110001ULL, ImplicitList16, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #705 = CMP64i32
18394 { 706, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x204011002fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #706 = CMP64mi32
18395 { 707, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x20c003002fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #707 = CMP64mi8
18396 { 708, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xe40010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #708 = CMP64mr
18397 { 709, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x204011003fULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr }, // Inst #709 = CMP64ri32
18398 { 710, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x20c003003fULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr }, // Inst #710 = CMP64ri8
18399 { 711, 6, 0, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xec0010021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #711 = CMP64rm
18400 { 712, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xe40010030ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #712 = CMP64rr
18401 { 713, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xec0010031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #713 = CMP64rr_REV
18402 { 714, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xf00020001ULL, ImplicitList11, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #714 = CMP8i8
18403 { 715, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x200002002fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #715 = CMP8mi
18404 { 716, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x208002002fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #716 = CMP8mi8
18405 { 717, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xe00000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #717 = CMP8mr
18406 { 718, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x200002003fULL, nullptr, ImplicitList1, OperandInfo161, -1 ,nullptr }, // Inst #718 = CMP8ri
18407 { 719, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x208002003fULL, nullptr, ImplicitList1, OperandInfo161, -1 ,nullptr }, // Inst #719 = CMP8ri8
18408 { 720, 6, 0, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xe80000021ULL, nullptr, ImplicitList1, OperandInfo162, -1 ,nullptr }, // Inst #720 = CMP8rm
18409 { 721, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xe00000030ULL, nullptr, ImplicitList1, OperandInfo163, -1 ,nullptr }, // Inst #721 = CMP8rr
18410 { 722, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0xe80000031ULL, nullptr, ImplicitList1, OperandInfo163, -1 ,nullptr }, // Inst #722 = CMP8rr_REV
18437 { 749, 6, 0, 0, 658, 0|(1ULL<<MCID::MayLoad), 0xbc0002821ULL, nullptr, ImplicitList1, OperandInfo169, -1 ,nullptr }, // Inst #749 = COMISDrm
18438 { 750, 6, 0, 0, 658, 0|(1ULL<<MCID::MayLoad), 0xbc0002821ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #750 = COMISDrm_Int
18439 { 751, 2, 0, 0, 719, 0, 0xbc0002831ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr }, // Inst #751 = COMISDrr
18440 { 752, 2, 0, 0, 719, 0, 0xbc0002831ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #752 = COMISDrr_Int
18441 { 753, 6, 0, 0, 658, 0|(1ULL<<MCID::MayLoad), 0xbc0002021ULL, nullptr, ImplicitList1, OperandInfo171, -1 ,nullptr }, // Inst #753 = COMISSrm
18442 { 754, 6, 0, 0, 658, 0|(1ULL<<MCID::MayLoad), 0xbc0002021ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #754 = COMISSrm_Int
18443 { 755, 2, 0, 0, 719, 0, 0xbc0002031ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr }, // Inst #755 = COMISSrr
18444 { 756, 2, 0, 0, 719, 0, 0xbc0002031ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #756 = COMISSrr_Int
18535 { 847, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc00000a9ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #847 = DEC16m
18536 { 848, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc00000b9ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #848 = DEC16r
18537 { 849, 2, 1, 0, 1, 0, 0x1200000082ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #849 = DEC16r_alt
18538 { 850, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc0000129ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #850 = DEC32m
18539 { 851, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0000139ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #851 = DEC32r
18540 { 852, 2, 1, 0, 1, 0, 0x1200000102ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #852 = DEC32r_alt
18541 { 853, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc0010029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #853 = DEC64m
18542 { 854, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0010039ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #854 = DEC64r
18543 { 855, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3f80000029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #855 = DEC8m
18544 { 856, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3f80000039ULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #856 = DEC8r
18622 { 934, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005a21ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #934 = ENQCMD16
18623 { 935, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005c21ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #935 = ENQCMD32
18624 { 936, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005e21ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #936 = ENQCMD64
18625 { 937, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005221ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #937 = ENQCMDS16
18626 { 938, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005421ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #938 = ENQCMDS32
18627 { 939, 6, 0, 0, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e00005621ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #939 = ENQCMDS64
18674 { 986, 6, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #986 = FP32_TO_INT16_IN_MEM
18675 { 987, 6, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #987 = FP32_TO_INT32_IN_MEM
18676 { 988, 6, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo194, -1 ,nullptr }, // Inst #988 = FP32_TO_INT64_IN_MEM
18677 { 989, 6, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo195, -1 ,nullptr }, // Inst #989 = FP64_TO_INT16_IN_MEM
18678 { 990, 6, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo195, -1 ,nullptr }, // Inst #990 = FP64_TO_INT32_IN_MEM
18679 { 991, 6, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo195, -1 ,nullptr }, // Inst #991 = FP64_TO_INT64_IN_MEM
18680 { 992, 6, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo196, -1 ,nullptr }, // Inst #992 = FP80_TO_INT16_IN_MEM
18681 { 993, 6, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo196, -1 ,nullptr }, // Inst #993 = FP80_TO_INT32_IN_MEM
18682 { 994, 6, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo196, -1 ,nullptr }, // Inst #994 = FP80_TO_INT64_IN_MEM
18741 { 1053, 7, 1, 0, 154, 0|(1ULL<<MCID::MayLoad), 0x2bc00020a1ULL, nullptr, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #1053 = IMUL16rm
18742 { 1054, 7, 1, 0, 155, 0|(1ULL<<MCID::MayLoad), 0x1a400800a1ULL, nullptr, ImplicitList1, OperandInfo200, -1 ,nullptr }, // Inst #1054 = IMUL16rmi
18743 { 1055, 7, 1, 0, 155, 0|(1ULL<<MCID::MayLoad), 0x1ac00200a1ULL, nullptr, ImplicitList1, OperandInfo200, -1 ,nullptr }, // Inst #1055 = IMUL16rmi8
18744 { 1056, 3, 1, 0, 156, 0|(1ULL<<MCID::Commutable), 0x2bc00020b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #1056 = IMUL16rr
18745 { 1057, 3, 1, 0, 157, 0, 0x1a400800b1ULL, nullptr, ImplicitList1, OperandInfo201, -1 ,nullptr }, // Inst #1057 = IMUL16rri
18746 { 1058, 3, 1, 0, 157, 0, 0x1ac00200b1ULL, nullptr, ImplicitList1, OperandInfo201, -1 ,nullptr }, // Inst #1058 = IMUL16rri8
18749 { 1061, 7, 1, 0, 160, 0|(1ULL<<MCID::MayLoad), 0x2bc0002121ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #1061 = IMUL32rm
18750 { 1062, 7, 1, 0, 161, 0|(1ULL<<MCID::MayLoad), 0x1a400c0121ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #1062 = IMUL32rmi
18751 { 1063, 7, 1, 0, 161, 0|(1ULL<<MCID::MayLoad), 0x1ac0020121ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #1063 = IMUL32rmi8
18752 { 1064, 3, 1, 0, 162, 0|(1ULL<<MCID::Commutable), 0x2bc0002131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #1064 = IMUL32rr
18753 { 1065, 3, 1, 0, 163, 0, 0x1a400c0131ULL, nullptr, ImplicitList1, OperandInfo112, -1 ,nullptr }, // Inst #1065 = IMUL32rri
18754 { 1066, 3, 1, 0, 163, 0, 0x1ac0020131ULL, nullptr, ImplicitList1, OperandInfo112, -1 ,nullptr }, // Inst #1066 = IMUL32rri8
18757 { 1069, 7, 1, 0, 166, 0|(1ULL<<MCID::MayLoad), 0x2bc0012021ULL, nullptr, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #1069 = IMUL64rm
18758 { 1070, 7, 1, 0, 167, 0|(1ULL<<MCID::MayLoad), 0x1a40110021ULL, nullptr, ImplicitList1, OperandInfo113, -1 ,nullptr }, // Inst #1070 = IMUL64rmi32
18759 { 1071, 7, 1, 0, 167, 0|(1ULL<<MCID::MayLoad), 0x1ac0030021ULL, nullptr, ImplicitList1, OperandInfo113, -1 ,nullptr }, // Inst #1071 = IMUL64rmi8
18760 { 1072, 3, 1, 0, 168, 0|(1ULL<<MCID::Commutable), 0x2bc0012031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #1072 = IMUL64rr
18761 { 1073, 3, 1, 0, 169, 0, 0x1a40110031ULL, nullptr, ImplicitList1, OperandInfo114, -1 ,nullptr }, // Inst #1073 = IMUL64rri32
18762 { 1074, 3, 1, 0, 169, 0, 0x1ac0030031ULL, nullptr, ImplicitList1, OperandInfo114, -1 ,nullptr }, // Inst #1074 = IMUL64rri8
18771 { 1083, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc00000a8ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1083 = INC16m
18772 { 1084, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc00000b8ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #1084 = INC16r
18773 { 1085, 2, 1, 0, 1, 0, 0x1000000082ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #1085 = INC16r_alt
18774 { 1086, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc0000128ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1086 = INC32m
18775 { 1087, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0000138ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #1087 = INC32r
18776 { 1088, 2, 1, 0, 1, 0, 0x1000000102ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #1088 = INC32r_alt
18777 { 1089, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc0010028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1089 = INC64m
18778 { 1090, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0010038ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #1090 = INC64r
18779 { 1091, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3f80000028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1091 = INC8m
18780 { 1092, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3f80000038ULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #1092 = INC8r
18792 { 1104, 0, 0, 0, 636, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3380000001ULL, ImplicitList1, nullptr, nullptr, -1 ,nullptr }, // Inst #1104 = INTO
18835 { 1147, 2, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x1c00040009ULL, ImplicitList1, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1147 = JCC_1
18836 { 1148, 2, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x20000a2089ULL, ImplicitList1, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1148 = JCC_2
18837 { 1149, 2, 0, 0, 7, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x20000e2109ULL, ImplicitList1, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1149 = JCC_4
18897 { 1209, 2, 0, 0, 1090, 0, 0x2610002831ULL, nullptr, ImplicitList1, OperandInfo209, -1 ,nullptr }, // Inst #1209 = KORTESTBrr
18898 { 1210, 2, 0, 0, 1090, 0, 0x6610002831ULL, nullptr, ImplicitList1, OperandInfo214, -1 ,nullptr }, // Inst #1210 = KORTESTDrr
18899 { 1211, 2, 0, 0, 1090, 0, 0x6610002031ULL, nullptr, ImplicitList1, OperandInfo219, -1 ,nullptr }, // Inst #1211 = KORTESTQrr
18900 { 1212, 2, 0, 0, 1090, 0, 0x2610002031ULL, nullptr, ImplicitList1, OperandInfo224, -1 ,nullptr }, // Inst #1212 = KORTESTWrr
18910 { 1222, 2, 0, 0, 1090, 0, 0x2650002831ULL, nullptr, ImplicitList1, OperandInfo209, -1 ,nullptr }, // Inst #1222 = KTESTBrr
18911 { 1223, 2, 0, 0, 1090, 0, 0x6650002831ULL, nullptr, ImplicitList1, OperandInfo214, -1 ,nullptr }, // Inst #1223 = KTESTDrr
18912 { 1224, 2, 0, 0, 1090, 0, 0x6650002031ULL, nullptr, ImplicitList1, OperandInfo219, -1 ,nullptr }, // Inst #1224 = KTESTQrr
18913 { 1225, 2, 0, 0, 1090, 0, 0x2650002031ULL, nullptr, ImplicitList1, OperandInfo224, -1 ,nullptr }, // Inst #1225 = KTESTWrr
18925 { 1237, 0, 0, 0, 943, 0, 0x27c0000001ULL, ImplicitList1, ImplicitList48, nullptr, -1 ,nullptr }, // Inst #1237 = LAHF
18987 { 1299, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410800a8ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1299 = LOCK_ADD16mi
18988 { 1300, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c10200a8ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1300 = LOCK_ADD16mi8
18989 { 1301, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1301 = LOCK_ADD16mr
18990 { 1302, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410c0128ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1302 = LOCK_ADD32mi
18991 { 1303, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c1020128ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1303 = LOCK_ADD32mi8
18992 { 1304, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x41000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1304 = LOCK_ADD32mr
18993 { 1305, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2041110028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1305 = LOCK_ADD64mi32
18994 { 1306, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c1030028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1306 = LOCK_ADD64mi8
18995 { 1307, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x41010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1307 = LOCK_ADD64mr
18996 { 1308, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2001020028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1308 = LOCK_ADD8mi
18997 { 1309, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #1309 = LOCK_ADD8mr
18998 { 1310, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410800acULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1310 = LOCK_AND16mi
18999 { 1311, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c10200acULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1311 = LOCK_AND16mi8
19000 { 1312, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x8410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1312 = LOCK_AND16mr
19001 { 1313, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410c012cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1313 = LOCK_AND32mi
19002 { 1314, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c102012cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1314 = LOCK_AND32mi8
19003 { 1315, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x841000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1315 = LOCK_AND32mr
19004 { 1316, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204111002cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1316 = LOCK_AND64mi32
19005 { 1317, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c103002cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1317 = LOCK_AND64mi8
19006 { 1318, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x841010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1318 = LOCK_AND64mr
19007 { 1319, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200102002cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1319 = LOCK_AND8mi
19008 { 1320, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x801000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #1320 = LOCK_AND8mr
19009 { 1321, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc10000a9ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1321 = LOCK_DEC16m
19010 { 1322, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc1000129ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1322 = LOCK_DEC32m
19011 { 1323, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc1010029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1323 = LOCK_DEC64m
19012 { 1324, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3f81000029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1324 = LOCK_DEC8m
19013 { 1325, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc10000a8ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1325 = LOCK_INC16m
19014 { 1326, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc1000128ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1326 = LOCK_INC32m
19015 { 1327, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3fc1010028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1327 = LOCK_INC64m
19016 { 1328, 5, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3f81000028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1328 = LOCK_INC8m
19017 { 1329, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410800a9ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1329 = LOCK_OR16mi
19018 { 1330, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c10200a9ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1330 = LOCK_OR16mi8
19019 { 1331, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1331 = LOCK_OR16mr
19020 { 1332, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410c0129ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1332 = LOCK_OR32mi
19021 { 1333, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c1020129ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1333 = LOCK_OR32mi8
19022 { 1334, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x241000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1334 = LOCK_OR32mr
19023 { 1335, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2041110029ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1335 = LOCK_OR64mi32
19024 { 1336, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c1030029ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1336 = LOCK_OR64mi8
19025 { 1337, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x241010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1337 = LOCK_OR64mr
19026 { 1338, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2001020029ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1338 = LOCK_OR8mi
19027 { 1339, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x201000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #1339 = LOCK_OR8mr
19029 { 1341, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410800adULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1341 = LOCK_SUB16mi
19030 { 1342, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c10200adULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1342 = LOCK_SUB16mi8
19031 { 1343, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1343 = LOCK_SUB16mr
19032 { 1344, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410c012dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1344 = LOCK_SUB32mi
19033 { 1345, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c102012dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1345 = LOCK_SUB32mi8
19034 { 1346, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa41000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1346 = LOCK_SUB32mr
19035 { 1347, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204111002dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1347 = LOCK_SUB64mi32
19036 { 1348, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c103002dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1348 = LOCK_SUB64mi8
19037 { 1349, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa41010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1349 = LOCK_SUB64mr
19038 { 1350, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200102002dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1350 = LOCK_SUB8mi
19039 { 1351, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa01000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #1351 = LOCK_SUB8mr
19040 { 1352, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410800aeULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1352 = LOCK_XOR16mi
19041 { 1353, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c10200aeULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1353 = LOCK_XOR16mi8
19042 { 1354, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc410000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1354 = LOCK_XOR16mr
19043 { 1355, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20410c012eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1355 = LOCK_XOR32mi
19044 { 1356, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c102012eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1356 = LOCK_XOR32mi8
19045 { 1357, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc41000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1357 = LOCK_XOR32mr
19046 { 1358, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204111002eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1358 = LOCK_XOR64mi32
19047 { 1359, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c103002eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1359 = LOCK_XOR64mi8
19048 { 1360, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc41010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1360 = LOCK_XOR64mr
19049 { 1361, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200102002eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1361 = LOCK_XOR8mi
19050 { 1362, 6, 0, 0, 19, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc01000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #1362 = LOCK_XOR8mr
19075 { 1387, 7, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84a00cc028ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #1387 = LWPINS32rmi
19076 { 1388, 3, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84a00cc038ULL, nullptr, ImplicitList1, OperandInfo112, -1 ,nullptr }, // Inst #1388 = LWPINS32rri
19077 { 1389, 7, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc4a00cc028ULL, nullptr, ImplicitList1, OperandInfo113, -1 ,nullptr }, // Inst #1389 = LWPINS64rmi
19078 { 1390, 3, 0, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc4a00cc038ULL, nullptr, ImplicitList1, OperandInfo243, -1 ,nullptr }, // Inst #1390 = LWPINS64rri
19083 { 1395, 7, 1, 0, 1002, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x30410020a1ULL, nullptr, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #1395 = LXADD16
19084 { 1396, 7, 1, 0, 1002, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3041002121ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #1396 = LXADD32
19085 { 1397, 7, 1, 0, 1002, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3041012021ULL, nullptr, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #1397 = LXADD64
19086 { 1398, 7, 1, 0, 1002, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3001002021ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #1398 = LXADD8
19087 { 1399, 6, 1, 0, 183, 0|(1ULL<<MCID::MayLoad), 0x2f400030a1ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #1399 = LZCNT16rm
19088 { 1400, 2, 1, 0, 184, 0, 0x2f400030b1ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #1400 = LZCNT16rr
19089 { 1401, 6, 1, 0, 183, 0|(1ULL<<MCID::MayLoad), 0x2f40003121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #1401 = LZCNT32rm
19090 { 1402, 2, 1, 0, 184, 0, 0x2f40003131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #1402 = LZCNT32rr
19091 { 1403, 6, 1, 0, 183, 0|(1ULL<<MCID::MayLoad), 0x2f40013021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #1403 = LZCNT64rm
19092 { 1404, 2, 1, 0, 184, 0, 0x2f40013031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #1404 = LZCNT64rr
19575 { 1887, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3dc00000abULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1887 = NEG16m
19576 { 1888, 2, 1, 0, 1, 0, 0x3dc00000bbULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #1888 = NEG16r
19577 { 1889, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3dc000012bULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1889 = NEG32m
19578 { 1890, 2, 1, 0, 1, 0, 0x3dc000013bULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #1890 = NEG32r
19579 { 1891, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3dc001002bULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1891 = NEG64m
19580 { 1892, 2, 1, 0, 1, 0, 0x3dc001003bULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #1892 = NEG64r
19581 { 1893, 5, 0, 0, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3d8000002bULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #1893 = NEG8m
19582 { 1894, 2, 1, 0, 1, 0, 0x3d8000003bULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #1894 = NEG8r
19599 { 1911, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400800a9ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1911 = OR16mi
19600 { 1912, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c00200a9ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1912 = OR16mi8
19601 { 1913, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #1913 = OR16mr
19602 { 1914, 3, 1, 0, 1, 0, 0x20400800b9ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #1914 = OR16ri
19603 { 1915, 3, 1, 0, 1, 0, 0x20c00200b9ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #1915 = OR16ri8
19604 { 1916, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0x2c00000a1ULL, nullptr, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #1916 = OR16rm
19605 { 1917, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x2400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #1917 = OR16rr
19606 { 1918, 3, 1, 0, 1, 0, 0x2c00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #1918 = OR16rr_REV
19608 { 1920, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400c0129ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1920 = OR32mi
19609 { 1921, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c0020129ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1921 = OR32mi8
19610 { 1922, 6, 0, 0, 954, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x20c1020129ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1922 = OR32mi8Locked
19611 { 1923, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x240000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #1923 = OR32mr
19612 { 1924, 3, 1, 0, 1, 0, 0x20400c0139ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #1924 = OR32ri
19613 { 1925, 3, 1, 0, 1, 0, 0x20c0020139ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #1925 = OR32ri8
19614 { 1926, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0x2c0000121ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #1926 = OR32rm
19615 { 1927, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x240000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #1927 = OR32rr
19616 { 1928, 3, 1, 0, 1, 0, 0x2c0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #1928 = OR32rr_REV
19618 { 1930, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2040110029ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1930 = OR64mi32
19619 { 1931, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c0030029ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1931 = OR64mi8
19620 { 1932, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x240010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #1932 = OR64mr
19621 { 1933, 3, 1, 0, 1, 0, 0x2040110039ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #1933 = OR64ri32
19622 { 1934, 3, 1, 0, 1, 0, 0x20c0030039ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #1934 = OR64ri8
19623 { 1935, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0x2c0010021ULL, nullptr, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #1935 = OR64rm
19624 { 1936, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x240010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #1936 = OR64rr
19625 { 1937, 3, 1, 0, 1, 0, 0x2c0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #1937 = OR64rr_REV
19627 { 1939, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2000020029ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1939 = OR8mi
19628 { 1940, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2080020029ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #1940 = OR8mi8
19629 { 1941, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #1941 = OR8mr
19630 { 1942, 3, 1, 0, 1, 0, 0x2000020039ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #1942 = OR8ri
19631 { 1943, 3, 1, 0, 1, 0, 0x2080020039ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #1943 = OR8ri8
19632 { 1944, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0x280000021ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #1944 = OR8rm
19633 { 1945, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0x200000030ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #1945 = OR8rr
19634 { 1946, 3, 1, 0, 1, 0, 0x280000031ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #1946 = OR8rr_REV
19883 { 2195, 6, 1, 0, 268, 0|(1ULL<<MCID::MayLoad), 0x2e000030a1ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #2195 = POPCNT16rm
19884 { 2196, 2, 1, 0, 269, 0, 0x2e000030b1ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #2196 = POPCNT16rr
19885 { 2197, 6, 1, 0, 268, 0|(1ULL<<MCID::MayLoad), 0x2e00003121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #2197 = POPCNT32rm
19886 { 2198, 2, 1, 0, 269, 0, 0x2e00003131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2198 = POPCNT32rr
19887 { 2199, 6, 1, 0, 268, 0|(1ULL<<MCID::MayLoad), 0x2e00013021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #2199 = POPCNT64rm
19888 { 2200, 2, 1, 0, 269, 0, 0x2e00013031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2200 = POPCNT64rr
19973 { 2285, 6, 0, 0, 277, 0|(1ULL<<MCID::MayLoad), 0x5cc004821ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #2285 = PTESTrm
19974 { 2286, 2, 0, 0, 278, 0, 0x5cc004831ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #2286 = PTESTrr
20031 { 2343, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x34400000aaULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2343 = RCL16m1
20031 { 2343, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x34400000aaULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2343 = RCL16m1
20032 { 2344, 5, 0, 0, 897, 0|(1ULL<<MCID::MayStore), 0x34c00000aaULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2344 = RCL16mCL
20033 { 2345, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x30400200aaULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2345 = RCL16mi
20033 { 2345, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x30400200aaULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2345 = RCL16mi
20034 { 2346, 2, 1, 0, 726, 0, 0x34400000baULL, ImplicitList1, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2346 = RCL16r1
20034 { 2346, 2, 1, 0, 726, 0, 0x34400000baULL, ImplicitList1, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2346 = RCL16r1
20035 { 2347, 2, 1, 0, 1013, 0, 0x34c00000baULL, ImplicitList78, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2347 = RCL16rCL
20036 { 2348, 3, 1, 0, 1018, 0, 0x30400200baULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2348 = RCL16ri
20036 { 2348, 3, 1, 0, 1018, 0, 0x30400200baULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2348 = RCL16ri
20037 { 2349, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344000012aULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2349 = RCL32m1
20037 { 2349, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344000012aULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2349 = RCL32m1
20038 { 2350, 5, 0, 0, 897, 0|(1ULL<<MCID::MayStore), 0x34c000012aULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2350 = RCL32mCL
20039 { 2351, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x304002012aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2351 = RCL32mi
20039 { 2351, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x304002012aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2351 = RCL32mi
20040 { 2352, 2, 1, 0, 726, 0, 0x344000013aULL, ImplicitList1, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2352 = RCL32r1
20040 { 2352, 2, 1, 0, 726, 0, 0x344000013aULL, ImplicitList1, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2352 = RCL32r1
20041 { 2353, 2, 1, 0, 1015, 0, 0x34c000013aULL, ImplicitList78, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2353 = RCL32rCL
20042 { 2354, 3, 1, 0, 1019, 0, 0x304002013aULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2354 = RCL32ri
20042 { 2354, 3, 1, 0, 1019, 0, 0x304002013aULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2354 = RCL32ri
20043 { 2355, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344001002aULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2355 = RCL64m1
20043 { 2355, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344001002aULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2355 = RCL64m1
20044 { 2356, 5, 0, 0, 897, 0|(1ULL<<MCID::MayStore), 0x34c001002aULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2356 = RCL64mCL
20045 { 2357, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x304003002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2357 = RCL64mi
20045 { 2357, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x304003002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2357 = RCL64mi
20046 { 2358, 2, 1, 0, 726, 0, 0x344001003aULL, ImplicitList1, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2358 = RCL64r1
20046 { 2358, 2, 1, 0, 726, 0, 0x344001003aULL, ImplicitList1, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2358 = RCL64r1
20047 { 2359, 2, 1, 0, 1015, 0, 0x34c001003aULL, ImplicitList78, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2359 = RCL64rCL
20048 { 2360, 3, 1, 0, 1019, 0, 0x304003003aULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2360 = RCL64ri
20048 { 2360, 3, 1, 0, 1019, 0, 0x304003003aULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2360 = RCL64ri
20049 { 2361, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x340000002aULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2361 = RCL8m1
20049 { 2361, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x340000002aULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2361 = RCL8m1
20050 { 2362, 5, 0, 0, 897, 0|(1ULL<<MCID::MayStore), 0x348000002aULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2362 = RCL8mCL
20051 { 2363, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x300002002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2363 = RCL8mi
20051 { 2363, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x300002002aULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2363 = RCL8mi
20052 { 2364, 2, 1, 0, 726, 0, 0x340000003aULL, ImplicitList1, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2364 = RCL8r1
20052 { 2364, 2, 1, 0, 726, 0, 0x340000003aULL, ImplicitList1, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2364 = RCL8r1
20053 { 2365, 2, 1, 0, 899, 0, 0x348000003aULL, ImplicitList78, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2365 = RCL8rCL
20054 { 2366, 3, 1, 0, 731, 0, 0x300002003aULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2366 = RCL8ri
20054 { 2366, 3, 1, 0, 731, 0, 0x300002003aULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2366 = RCL8ri
20061 { 2373, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x34400000abULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2373 = RCR16m1
20061 { 2373, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x34400000abULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2373 = RCR16m1
20062 { 2374, 5, 0, 0, 584, 0|(1ULL<<MCID::MayStore), 0x34c00000abULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2374 = RCR16mCL
20063 { 2375, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x30400200abULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2375 = RCR16mi
20063 { 2375, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x30400200abULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2375 = RCR16mi
20064 { 2376, 2, 1, 0, 726, 0, 0x34400000bbULL, ImplicitList1, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2376 = RCR16r1
20064 { 2376, 2, 1, 0, 726, 0, 0x34400000bbULL, ImplicitList1, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2376 = RCR16r1
20065 { 2377, 2, 1, 0, 898, 0, 0x34c00000bbULL, ImplicitList78, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2377 = RCR16rCL
20066 { 2378, 3, 1, 0, 1014, 0, 0x30400200bbULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2378 = RCR16ri
20066 { 2378, 3, 1, 0, 1014, 0, 0x30400200bbULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2378 = RCR16ri
20067 { 2379, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344000012bULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2379 = RCR32m1
20067 { 2379, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344000012bULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2379 = RCR32m1
20068 { 2380, 5, 0, 0, 584, 0|(1ULL<<MCID::MayStore), 0x34c000012bULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2380 = RCR32mCL
20069 { 2381, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x304002012bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2381 = RCR32mi
20069 { 2381, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x304002012bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2381 = RCR32mi
20070 { 2382, 2, 1, 0, 726, 0, 0x344000013bULL, ImplicitList1, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2382 = RCR32r1
20070 { 2382, 2, 1, 0, 726, 0, 0x344000013bULL, ImplicitList1, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2382 = RCR32r1
20071 { 2383, 2, 1, 0, 1016, 0, 0x34c000013bULL, ImplicitList78, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2383 = RCR32rCL
20072 { 2384, 3, 1, 0, 1017, 0, 0x304002013bULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2384 = RCR32ri
20072 { 2384, 3, 1, 0, 1017, 0, 0x304002013bULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2384 = RCR32ri
20073 { 2385, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344001002bULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2385 = RCR64m1
20073 { 2385, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x344001002bULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2385 = RCR64m1
20074 { 2386, 5, 0, 0, 584, 0|(1ULL<<MCID::MayStore), 0x34c001002bULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2386 = RCR64mCL
20075 { 2387, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x304003002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2387 = RCR64mi
20075 { 2387, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x304003002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2387 = RCR64mi
20076 { 2388, 2, 1, 0, 726, 0, 0x344001003bULL, ImplicitList1, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2388 = RCR64r1
20076 { 2388, 2, 1, 0, 726, 0, 0x344001003bULL, ImplicitList1, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2388 = RCR64r1
20077 { 2389, 2, 1, 0, 1016, 0, 0x34c001003bULL, ImplicitList78, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2389 = RCR64rCL
20078 { 2390, 3, 1, 0, 1017, 0, 0x304003003bULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2390 = RCR64ri
20078 { 2390, 3, 1, 0, 1017, 0, 0x304003003bULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2390 = RCR64ri
20079 { 2391, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x340000002bULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2391 = RCR8m1
20079 { 2391, 5, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x340000002bULL, ImplicitList1, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2391 = RCR8m1
20080 { 2392, 5, 0, 0, 584, 0|(1ULL<<MCID::MayStore), 0x348000002bULL, ImplicitList78, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2392 = RCR8mCL
20081 { 2393, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x300002002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2393 = RCR8mi
20081 { 2393, 6, 0, 0, 583, 0|(1ULL<<MCID::MayStore), 0x300002002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2393 = RCR8mi
20082 { 2394, 2, 1, 0, 726, 0, 0x340000003bULL, ImplicitList1, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2394 = RCR8r1
20082 { 2394, 2, 1, 0, 726, 0, 0x340000003bULL, ImplicitList1, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2394 = RCR8r1
20083 { 2395, 2, 1, 0, 730, 0, 0x348000003bULL, ImplicitList78, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2395 = RCR8rCL
20084 { 2396, 3, 1, 0, 1012, 0, 0x300002003bULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2396 = RCR8ri
20084 { 2396, 3, 1, 0, 1012, 0, 0x300002003bULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2396 = RCR8ri
20096 { 2408, 1, 1, 0, 799, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c00020beULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #2408 = RDRAND16r
20097 { 2409, 1, 1, 0, 799, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c000213eULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #2409 = RDRAND32r
20098 { 2410, 1, 1, 0, 799, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c001203eULL, nullptr, ImplicitList1, OperandInfo64, -1 ,nullptr }, // Inst #2410 = RDRAND64r
20099 { 2411, 1, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c00020bfULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr }, // Inst #2411 = RDSEED16r
20100 { 2412, 1, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c000213fULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #2412 = RDSEED32r
20101 { 2413, 1, 1, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x31c001203fULL, nullptr, ImplicitList1, OperandInfo64, -1 ,nullptr }, // Inst #2413 = RDSEED64r
20132 { 2444, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000a8ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2444 = ROL16m1
20133 { 2445, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000a8ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2445 = ROL16mCL
20134 { 2446, 6, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x30400200a8ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2446 = ROL16mi
20135 { 2447, 2, 1, 0, 848, 0, 0x34400000b8ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2447 = ROL16r1
20136 { 2448, 2, 1, 0, 282, 0, 0x34c00000b8ULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2448 = ROL16rCL
20137 { 2449, 3, 1, 0, 281, 0, 0x30400200b8ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2449 = ROL16ri
20138 { 2450, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3440000128ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2450 = ROL32m1
20139 { 2451, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0000128ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2451 = ROL32mCL
20140 { 2452, 6, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3040020128ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2452 = ROL32mi
20141 { 2453, 2, 1, 0, 848, 0, 0x3440000138ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2453 = ROL32r1
20142 { 2454, 2, 1, 0, 282, 0, 0x34c0000138ULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2454 = ROL32rCL
20143 { 2455, 3, 1, 0, 281, 0, 0x3040020138ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2455 = ROL32ri
20144 { 2456, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3440010028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2456 = ROL64m1
20145 { 2457, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0010028ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2457 = ROL64mCL
20146 { 2458, 6, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3040030028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2458 = ROL64mi
20147 { 2459, 2, 1, 0, 848, 0, 0x3440010038ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2459 = ROL64r1
20148 { 2460, 2, 1, 0, 282, 0, 0x34c0010038ULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2460 = ROL64rCL
20149 { 2461, 3, 1, 0, 281, 0, 0x3040030038ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2461 = ROL64ri
20150 { 2462, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3400000028ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2462 = ROL8m1
20151 { 2463, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3480000028ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2463 = ROL8mCL
20152 { 2464, 6, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3000020028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2464 = ROL8mi
20153 { 2465, 2, 1, 0, 848, 0, 0x3400000038ULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2465 = ROL8r1
20154 { 2466, 2, 1, 0, 282, 0, 0x3480000038ULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2466 = ROL8rCL
20155 { 2467, 3, 1, 0, 281, 0, 0x3000020038ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2467 = ROL8ri
20156 { 2468, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000a9ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2468 = ROR16m1
20157 { 2469, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000a9ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2469 = ROR16mCL
20158 { 2470, 6, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x30400200a9ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2470 = ROR16mi
20159 { 2471, 2, 1, 0, 848, 0, 0x34400000b9ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2471 = ROR16r1
20160 { 2472, 2, 1, 0, 282, 0, 0x34c00000b9ULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2472 = ROR16rCL
20161 { 2473, 3, 1, 0, 281, 0, 0x30400200b9ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2473 = ROR16ri
20162 { 2474, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3440000129ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2474 = ROR32m1
20163 { 2475, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0000129ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2475 = ROR32mCL
20164 { 2476, 6, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3040020129ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2476 = ROR32mi
20165 { 2477, 2, 1, 0, 848, 0, 0x3440000139ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2477 = ROR32r1
20166 { 2478, 2, 1, 0, 282, 0, 0x34c0000139ULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2478 = ROR32rCL
20167 { 2479, 3, 1, 0, 281, 0, 0x3040020139ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2479 = ROR32ri
20168 { 2480, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3440010029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2480 = ROR64m1
20169 { 2481, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c0010029ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2481 = ROR64mCL
20170 { 2482, 6, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3040030029ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2482 = ROR64mi
20171 { 2483, 2, 1, 0, 848, 0, 0x3440010039ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2483 = ROR64r1
20172 { 2484, 2, 1, 0, 282, 0, 0x34c0010039ULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2484 = ROR64rCL
20173 { 2485, 3, 1, 0, 281, 0, 0x3040030039ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2485 = ROR64ri
20174 { 2486, 5, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3400000029ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2486 = ROR8m1
20175 { 2487, 5, 0, 0, 771, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3480000029ULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2487 = ROR8mCL
20176 { 2488, 6, 0, 0, 765, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3000020029ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2488 = ROR8mi
20177 { 2489, 2, 1, 0, 848, 0, 0x3400000039ULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2489 = ROR8r1
20178 { 2490, 2, 1, 0, 282, 0, 0x3480000039ULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2490 = ROR8rCL
20179 { 2491, 3, 1, 0, 281, 0, 0x3000020039ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2491 = ROR8ri
20204 { 2516, 0, 0, 0, 1009, 0, 0x2780000001ULL, ImplicitList48, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2516 = SAHF
20205 { 2517, 0, 0, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3580000001ULL, ImplicitList1, ImplicitList11, nullptr, -1 ,nullptr }, // Inst #2517 = SALC
20206 { 2518, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000afULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2518 = SAR16m1
20207 { 2519, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000afULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2519 = SAR16mCL
20208 { 2520, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x30400200afULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2520 = SAR16mi
20209 { 2521, 2, 1, 0, 290, 0, 0x34400000bfULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2521 = SAR16r1
20210 { 2522, 2, 1, 0, 301, 0, 0x34c00000bfULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2522 = SAR16rCL
20211 { 2523, 3, 1, 0, 290, 0, 0x30400200bfULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2523 = SAR16ri
20212 { 2524, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344000012fULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2524 = SAR32m1
20213 { 2525, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c000012fULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2525 = SAR32mCL
20214 { 2526, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x304002012fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2526 = SAR32mi
20215 { 2527, 2, 1, 0, 290, 0, 0x344000013fULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2527 = SAR32r1
20216 { 2528, 2, 1, 0, 301, 0, 0x34c000013fULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2528 = SAR32rCL
20217 { 2529, 3, 1, 0, 290, 0, 0x304002013fULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2529 = SAR32ri
20218 { 2530, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344001002fULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2530 = SAR64m1
20219 { 2531, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c001002fULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2531 = SAR64mCL
20220 { 2532, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x304003002fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2532 = SAR64mi
20221 { 2533, 2, 1, 0, 290, 0, 0x344001003fULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2533 = SAR64r1
20222 { 2534, 2, 1, 0, 301, 0, 0x34c001003fULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2534 = SAR64rCL
20223 { 2535, 3, 1, 0, 290, 0, 0x304003003fULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2535 = SAR64ri
20224 { 2536, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x340000002fULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2536 = SAR8m1
20225 { 2537, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x348000002fULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2537 = SAR8mCL
20226 { 2538, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x300002002fULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2538 = SAR8mi
20227 { 2539, 2, 1, 0, 290, 0, 0x340000003fULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2539 = SAR8r1
20228 { 2540, 2, 1, 0, 301, 0, 0x348000003fULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2540 = SAR8rCL
20229 { 2541, 3, 1, 0, 290, 0, 0x300002003fULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2541 = SAR8ri
20236 { 2548, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400800abULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2548 = SBB16mi
20236 { 2548, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400800abULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2548 = SBB16mi
20237 { 2549, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c00200abULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2549 = SBB16mi8
20237 { 2549, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c00200abULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2549 = SBB16mi8
20238 { 2550, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x6400000a0ULL, ImplicitList1, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2550 = SBB16mr
20238 { 2550, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x6400000a0ULL, ImplicitList1, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2550 = SBB16mr
20239 { 2551, 3, 1, 0, 16, 0, 0x20400800bbULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2551 = SBB16ri
20239 { 2551, 3, 1, 0, 16, 0, 0x20400800bbULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2551 = SBB16ri
20240 { 2552, 3, 1, 0, 925, 0, 0x20c00200bbULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2552 = SBB16ri8
20240 { 2552, 3, 1, 0, 925, 0, 0x20c00200bbULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2552 = SBB16ri8
20241 { 2553, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x6c00000a1ULL, ImplicitList1, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #2553 = SBB16rm
20241 { 2553, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x6c00000a1ULL, ImplicitList1, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #2553 = SBB16rm
20242 { 2554, 3, 1, 0, 16, 0, 0x6400000b0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2554 = SBB16rr
20242 { 2554, 3, 1, 0, 16, 0, 0x6400000b0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2554 = SBB16rr
20243 { 2555, 3, 1, 0, 16, 0, 0x6c00000b1ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2555 = SBB16rr_REV
20243 { 2555, 3, 1, 0, 16, 0, 0x6c00000b1ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2555 = SBB16rr_REV
20245 { 2557, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400c012bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2557 = SBB32mi
20245 { 2557, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400c012bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2557 = SBB32mi
20246 { 2558, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c002012bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2558 = SBB32mi8
20246 { 2558, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c002012bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2558 = SBB32mi8
20247 { 2559, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x640000120ULL, ImplicitList1, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2559 = SBB32mr
20247 { 2559, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x640000120ULL, ImplicitList1, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2559 = SBB32mr
20248 { 2560, 3, 1, 0, 16, 0, 0x20400c013bULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2560 = SBB32ri
20248 { 2560, 3, 1, 0, 16, 0, 0x20400c013bULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2560 = SBB32ri
20249 { 2561, 3, 1, 0, 925, 0, 0x20c002013bULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2561 = SBB32ri8
20249 { 2561, 3, 1, 0, 925, 0, 0x20c002013bULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2561 = SBB32ri8
20250 { 2562, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x6c0000121ULL, ImplicitList1, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #2562 = SBB32rm
20250 { 2562, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x6c0000121ULL, ImplicitList1, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #2562 = SBB32rm
20251 { 2563, 3, 1, 0, 16, 0, 0x640000130ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2563 = SBB32rr
20251 { 2563, 3, 1, 0, 16, 0, 0x640000130ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2563 = SBB32rr
20252 { 2564, 3, 1, 0, 16, 0, 0x6c0000131ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2564 = SBB32rr_REV
20252 { 2564, 3, 1, 0, 16, 0, 0x6c0000131ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2564 = SBB32rr_REV
20254 { 2566, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204011002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2566 = SBB64mi32
20254 { 2566, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204011002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2566 = SBB64mi32
20255 { 2567, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c003002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2567 = SBB64mi8
20255 { 2567, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c003002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2567 = SBB64mi8
20256 { 2568, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x640010020ULL, ImplicitList1, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2568 = SBB64mr
20256 { 2568, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x640010020ULL, ImplicitList1, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2568 = SBB64mr
20257 { 2569, 3, 1, 0, 1005, 0, 0x204011003bULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2569 = SBB64ri32
20257 { 2569, 3, 1, 0, 1005, 0, 0x204011003bULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2569 = SBB64ri32
20258 { 2570, 3, 1, 0, 925, 0, 0x20c003003bULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2570 = SBB64ri8
20258 { 2570, 3, 1, 0, 925, 0, 0x20c003003bULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2570 = SBB64ri8
20259 { 2571, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x6c0010021ULL, ImplicitList1, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #2571 = SBB64rm
20259 { 2571, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x6c0010021ULL, ImplicitList1, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #2571 = SBB64rm
20260 { 2572, 3, 1, 0, 16, 0, 0x640010030ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2572 = SBB64rr
20260 { 2572, 3, 1, 0, 16, 0, 0x640010030ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2572 = SBB64rr
20261 { 2573, 3, 1, 0, 16, 0, 0x6c0010031ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2573 = SBB64rr_REV
20261 { 2573, 3, 1, 0, 16, 0, 0x6c0010031ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2573 = SBB64rr_REV
20263 { 2575, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200002002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2575 = SBB8mi
20263 { 2575, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200002002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2575 = SBB8mi
20264 { 2576, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x208002002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2576 = SBB8mi8
20264 { 2576, 6, 0, 0, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x208002002bULL, ImplicitList1, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2576 = SBB8mi8
20265 { 2577, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x600000020ULL, ImplicitList1, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #2577 = SBB8mr
20265 { 2577, 6, 0, 0, 772, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x600000020ULL, ImplicitList1, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #2577 = SBB8mr
20266 { 2578, 3, 1, 0, 16, 0, 0x200002003bULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2578 = SBB8ri
20266 { 2578, 3, 1, 0, 16, 0, 0x200002003bULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2578 = SBB8ri
20267 { 2579, 3, 1, 0, 16, 0, 0x208002003bULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2579 = SBB8ri8
20267 { 2579, 3, 1, 0, 16, 0, 0x208002003bULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2579 = SBB8ri8
20268 { 2580, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x680000021ULL, ImplicitList1, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #2580 = SBB8rm
20268 { 2580, 7, 1, 0, 18, 0|(1ULL<<MCID::MayLoad), 0x680000021ULL, ImplicitList1, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #2580 = SBB8rm
20269 { 2581, 3, 1, 0, 16, 0, 0x600000030ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #2581 = SBB8rr
20269 { 2581, 3, 1, 0, 16, 0, 0x600000030ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #2581 = SBB8rr
20270 { 2582, 3, 1, 0, 16, 0, 0x680000031ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #2582 = SBB8rr_REV
20270 { 2582, 3, 1, 0, 16, 0, 0x680000031ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #2582 = SBB8rr_REV
20277 { 2589, 6, 0, 0, 794, 0|(1ULL<<MCID::MayStore), 0x2400002026ULL, ImplicitList1, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2589 = SETCCm
20278 { 2590, 2, 1, 0, 793, 0, 0x2400002036ULL, ImplicitList1, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #2590 = SETCCr
20298 { 2610, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000acULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2610 = SHL16m1
20299 { 2611, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000acULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2611 = SHL16mCL
20300 { 2612, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x30400200acULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2612 = SHL16mi
20301 { 2613, 2, 1, 0, 290, 0, 0x34400000bcULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2613 = SHL16r1
20302 { 2614, 2, 1, 0, 301, 0, 0x34c00000bcULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2614 = SHL16rCL
20303 { 2615, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x30400200bcULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2615 = SHL16ri
20304 { 2616, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344000012cULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2616 = SHL32m1
20305 { 2617, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c000012cULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2617 = SHL32mCL
20306 { 2618, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x304002012cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2618 = SHL32mi
20307 { 2619, 2, 1, 0, 290, 0, 0x344000013cULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2619 = SHL32r1
20308 { 2620, 2, 1, 0, 301, 0, 0x34c000013cULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2620 = SHL32rCL
20309 { 2621, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x304002013cULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2621 = SHL32ri
20310 { 2622, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344001002cULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2622 = SHL64m1
20311 { 2623, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c001002cULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2623 = SHL64mCL
20312 { 2624, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x304003002cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2624 = SHL64mi
20313 { 2625, 2, 1, 0, 290, 0, 0x344001003cULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2625 = SHL64r1
20314 { 2626, 2, 1, 0, 301, 0, 0x34c001003cULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2626 = SHL64rCL
20315 { 2627, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x304003003cULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2627 = SHL64ri
20316 { 2628, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x340000002cULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2628 = SHL8m1
20317 { 2629, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x348000002cULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2629 = SHL8mCL
20318 { 2630, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x300002002cULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2630 = SHL8mi
20319 { 2631, 2, 1, 0, 290, 0, 0x340000003cULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2631 = SHL8r1
20320 { 2632, 2, 1, 0, 301, 0, 0x348000003cULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2632 = SHL8rCL
20321 { 2633, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x300002003cULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2633 = SHL8ri
20322 { 2634, 6, 0, 0, 640, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x29400020a0ULL, ImplicitList90, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2634 = SHLD16mrCL
20323 { 2635, 7, 0, 0, 641, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x29000220a0ULL, nullptr, ImplicitList1, OperandInfo310, -1 ,nullptr }, // Inst #2635 = SHLD16mri8
20324 { 2636, 3, 1, 0, 1022, 0, 0x29400020b0ULL, ImplicitList90, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2636 = SHLD16rrCL
20325 { 2637, 4, 1, 0, 639, 0|(1ULL<<MCID::Commutable), 0x29000220b0ULL, nullptr, ImplicitList1, OperandInfo311, -1 ,nullptr }, // Inst #2637 = SHLD16rri8
20326 { 2638, 6, 0, 0, 957, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2940002120ULL, ImplicitList90, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2638 = SHLD32mrCL
20327 { 2639, 7, 0, 0, 955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2900022120ULL, nullptr, ImplicitList1, OperandInfo312, -1 ,nullptr }, // Inst #2639 = SHLD32mri8
20328 { 2640, 3, 1, 0, 956, 0, 0x2940002130ULL, ImplicitList90, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2640 = SHLD32rrCL
20329 { 2641, 4, 1, 0, 1020, 0|(1ULL<<MCID::Commutable), 0x2900022130ULL, nullptr, ImplicitList1, OperandInfo313, -1 ,nullptr }, // Inst #2641 = SHLD32rri8
20330 { 2642, 6, 0, 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2940012020ULL, ImplicitList90, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2642 = SHLD64mrCL
20331 { 2643, 7, 0, 0, 652, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2900032020ULL, nullptr, ImplicitList1, OperandInfo314, -1 ,nullptr }, // Inst #2643 = SHLD64mri8
20332 { 2644, 3, 1, 0, 647, 0, 0x2940012030ULL, ImplicitList90, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2644 = SHLD64rrCL
20333 { 2645, 4, 1, 0, 653, 0|(1ULL<<MCID::Commutable), 0x2900032030ULL, nullptr, ImplicitList1, OperandInfo315, -1 ,nullptr }, // Inst #2645 = SHLD64rri8
20338 { 2650, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34400000adULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2650 = SHR16m1
20339 { 2651, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c00000adULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2651 = SHR16mCL
20340 { 2652, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x30400200adULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2652 = SHR16mi
20341 { 2653, 2, 1, 0, 290, 0, 0x34400000bdULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2653 = SHR16r1
20342 { 2654, 2, 1, 0, 301, 0, 0x34c00000bdULL, ImplicitList90, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #2654 = SHR16rCL
20343 { 2655, 3, 1, 0, 290, 0, 0x30400200bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2655 = SHR16ri
20344 { 2656, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344000012dULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2656 = SHR32m1
20345 { 2657, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c000012dULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2657 = SHR32mCL
20346 { 2658, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x304002012dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2658 = SHR32mi
20347 { 2659, 2, 1, 0, 290, 0, 0x344000013dULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2659 = SHR32r1
20348 { 2660, 2, 1, 0, 301, 0, 0x34c000013dULL, ImplicitList90, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #2660 = SHR32rCL
20349 { 2661, 3, 1, 0, 290, 0, 0x304002013dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2661 = SHR32ri
20350 { 2662, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x344001002dULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2662 = SHR64m1
20351 { 2663, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x34c001002dULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2663 = SHR64mCL
20352 { 2664, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x304003002dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2664 = SHR64mi
20353 { 2665, 2, 1, 0, 290, 0, 0x344001003dULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2665 = SHR64r1
20354 { 2666, 2, 1, 0, 301, 0, 0x34c001003dULL, ImplicitList90, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #2666 = SHR64rCL
20355 { 2667, 3, 1, 0, 290, 0, 0x304003003dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2667 = SHR64ri
20356 { 2668, 5, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x340000002dULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2668 = SHR8m1
20357 { 2669, 5, 0, 0, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x348000002dULL, ImplicitList90, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #2669 = SHR8mCL
20358 { 2670, 6, 0, 0, 585, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x300002002dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2670 = SHR8mi
20359 { 2671, 2, 1, 0, 290, 0, 0x340000003dULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2671 = SHR8r1
20360 { 2672, 2, 1, 0, 301, 0, 0x348000003dULL, ImplicitList90, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #2672 = SHR8rCL
20361 { 2673, 3, 1, 0, 290, 0, 0x300002003dULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2673 = SHR8ri
20362 { 2674, 6, 0, 0, 640, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b400020a0ULL, ImplicitList90, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2674 = SHRD16mrCL
20363 { 2675, 7, 0, 0, 641, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b000220a0ULL, nullptr, ImplicitList1, OperandInfo310, -1 ,nullptr }, // Inst #2675 = SHRD16mri8
20364 { 2676, 3, 1, 0, 638, 0, 0x2b400020b0ULL, ImplicitList90, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2676 = SHRD16rrCL
20365 { 2677, 4, 1, 0, 1021, 0|(1ULL<<MCID::Commutable), 0x2b000220b0ULL, nullptr, ImplicitList1, OperandInfo311, -1 ,nullptr }, // Inst #2677 = SHRD16rri8
20366 { 2678, 6, 0, 0, 957, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b40002120ULL, ImplicitList90, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2678 = SHRD32mrCL
20367 { 2679, 7, 0, 0, 955, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b00022120ULL, nullptr, ImplicitList1, OperandInfo312, -1 ,nullptr }, // Inst #2679 = SHRD32mri8
20368 { 2680, 3, 1, 0, 956, 0, 0x2b40002130ULL, ImplicitList90, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2680 = SHRD32rrCL
20369 { 2681, 4, 1, 0, 9, 0|(1ULL<<MCID::Commutable), 0x2b00022130ULL, nullptr, ImplicitList1, OperandInfo313, -1 ,nullptr }, // Inst #2681 = SHRD32rri8
20370 { 2682, 6, 0, 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b40012020ULL, ImplicitList90, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2682 = SHRD64mrCL
20371 { 2683, 7, 0, 0, 652, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2b00032020ULL, nullptr, ImplicitList1, OperandInfo314, -1 ,nullptr }, // Inst #2683 = SHRD64mri8
20372 { 2684, 3, 1, 0, 647, 0, 0x2b40012030ULL, ImplicitList90, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2684 = SHRD64rrCL
20373 { 2685, 4, 1, 0, 653, 0|(1ULL<<MCID::Commutable), 0x2b00032030ULL, nullptr, ImplicitList1, OperandInfo315, -1 ,nullptr }, // Inst #2685 = SHRD64rri8
20417 { 2729, 0, 0, 0, 1057, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4000204bULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2729 = STAC
20418 { 2730, 0, 0, 0, 821, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e40000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2730 = STC
20418 { 2730, 0, 0, 0, 821, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3e40000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2730 = STC
20421 { 2733, 0, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ec0000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2733 = STI
20421 { 2733, 0, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ec0000001ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2733 = STI
20450 { 2762, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400800adULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2762 = SUB16mi
20451 { 2763, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c00200adULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2763 = SUB16mi8
20452 { 2764, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2764 = SUB16mr
20453 { 2765, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400800bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2765 = SUB16ri
20454 { 2766, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c00200bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2766 = SUB16ri8
20455 { 2767, 7, 1, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xac00000a1ULL, nullptr, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #2767 = SUB16rm
20456 { 2768, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xa400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2768 = SUB16rr
20457 { 2769, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xac00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #2769 = SUB16rr_REV
20459 { 2771, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400c012dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2771 = SUB32mi
20460 { 2772, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c002012dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2772 = SUB32mi8
20461 { 2773, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa40000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2773 = SUB32mr
20462 { 2774, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400c013dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2774 = SUB32ri
20463 { 2775, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c002013dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2775 = SUB32ri8
20464 { 2776, 7, 1, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xac0000121ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #2776 = SUB32rm
20465 { 2777, 3, 1, 0, 784, 0|(1ULL<<MCID::Compare), 0xa40000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2777 = SUB32rr
20466 { 2778, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xac0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #2778 = SUB32rr_REV
20468 { 2780, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204011002dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2780 = SUB64mi32
20469 { 2781, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c003002dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2781 = SUB64mi8
20470 { 2782, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa40010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2782 = SUB64mr
20471 { 2783, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x204011003dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2783 = SUB64ri32
20472 { 2784, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c003003dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2784 = SUB64ri8
20473 { 2785, 7, 1, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xac0010021ULL, nullptr, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #2785 = SUB64rm
20474 { 2786, 3, 1, 0, 784, 0|(1ULL<<MCID::Compare), 0xa40010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2786 = SUB64rr
20475 { 2787, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xac0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #2787 = SUB64rr_REV
20477 { 2789, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200002002dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2789 = SUB8mi
20478 { 2790, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x208002002dULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2790 = SUB8mi8
20479 { 2791, 6, 0, 0, 944, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xa00000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #2791 = SUB8mr
20480 { 2792, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x200002003dULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2792 = SUB8ri
20481 { 2793, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0x208002003dULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2793 = SUB8ri8
20482 { 2794, 7, 1, 0, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0xa80000021ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #2794 = SUB8rm
20483 { 2795, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xa00000030ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #2795 = SUB8rr
20484 { 2796, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare), 0xa80000031ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #2796 = SUB8rr_REV
20543 { 2855, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02fULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #2855 = T1MSKC32rm
20544 { 2856, 2, 1, 0, 1003, 0, 0x806000a03fULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2856 = T1MSKC32rr
20545 { 2857, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02fULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #2857 = T1MSKC64rm
20546 { 2858, 2, 1, 0, 1003, 0, 0xc06000a03fULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2858 = T1MSKC64rr
20565 { 2877, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x2a40080081ULL, ImplicitList10, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #2877 = TEST16i16
20566 { 2878, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3dc00800a8ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2878 = TEST16mi
20567 { 2879, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x21400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #2879 = TEST16mr
20568 { 2880, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x3dc00800b8ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #2880 = TEST16ri
20569 { 2881, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x21400000b0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #2881 = TEST16rr
20570 { 2882, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x2a400c0101ULL, ImplicitList7, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #2882 = TEST32i32
20571 { 2883, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3dc00c0128ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2883 = TEST32mi
20572 { 2884, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x2140000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #2884 = TEST32mr
20573 { 2885, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x3dc00c0138ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr }, // Inst #2885 = TEST32ri
20574 { 2886, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2140000130ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2886 = TEST32rr
20575 { 2887, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x2a40110001ULL, ImplicitList16, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #2887 = TEST64i32
20576 { 2888, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3dc0110028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2888 = TEST64mi32
20577 { 2889, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x2140010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #2889 = TEST64mr
20578 { 2890, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x3dc0110038ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr }, // Inst #2890 = TEST64ri32
20579 { 2891, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2140010030ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2891 = TEST64rr
20580 { 2892, 1, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x2a00020001ULL, ImplicitList11, ImplicitList1, OperandInfo3, -1 ,nullptr }, // Inst #2892 = TEST8i8
20581 { 2893, 6, 0, 0, 41, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3d80020028ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #2893 = TEST8mi
20582 { 2894, 6, 0, 0, 66, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x2100000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #2894 = TEST8mr
20583 { 2895, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare), 0x3d80020038ULL, nullptr, ImplicitList1, OperandInfo161, -1 ,nullptr }, // Inst #2895 = TEST8ri
20584 { 2896, 2, 0, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable), 0x2100000030ULL, nullptr, ImplicitList1, OperandInfo163, -1 ,nullptr }, // Inst #2896 = TEST8rr
20591 { 2903, 1, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000283eULL, ImplicitList21, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #2903 = TPAUSE
20597 { 2909, 6, 1, 0, 320, 0|(1ULL<<MCID::MayLoad), 0x2f000030a1ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #2909 = TZCNT16rm
20598 { 2910, 2, 1, 0, 321, 0, 0x2f000030b1ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #2910 = TZCNT16rr
20599 { 2911, 6, 1, 0, 320, 0|(1ULL<<MCID::MayLoad), 0x2f00003121ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #2911 = TZCNT32rm
20600 { 2912, 2, 1, 0, 321, 0, 0x2f00003131ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2912 = TZCNT32rr
20601 { 2913, 6, 1, 0, 320, 0|(1ULL<<MCID::MayLoad), 0x2f00013021ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #2913 = TZCNT64rm
20602 { 2914, 2, 1, 0, 321, 0, 0x2f00013031ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2914 = TZCNT64rr
20603 { 2915, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0x806000a02cULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #2915 = TZMSK32rm
20604 { 2916, 2, 1, 0, 1003, 0, 0x806000a03cULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #2916 = TZMSK32rr
20605 { 2917, 6, 1, 0, 1004, 0|(1ULL<<MCID::MayLoad), 0xc06000a02cULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr }, // Inst #2917 = TZMSK64rm
20606 { 2918, 2, 1, 0, 1003, 0, 0xc06000a03cULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr }, // Inst #2918 = TZMSK64rr
20607 { 2919, 6, 0, 0, 658, 0|(1ULL<<MCID::MayLoad), 0xb80002821ULL, nullptr, ImplicitList1, OperandInfo169, -1 ,nullptr }, // Inst #2919 = UCOMISDrm
20608 { 2920, 6, 0, 0, 658, 0|(1ULL<<MCID::MayLoad), 0xb80002821ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #2920 = UCOMISDrm_Int
20609 { 2921, 2, 0, 0, 719, 0, 0xb80002831ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr }, // Inst #2921 = UCOMISDrr
20610 { 2922, 2, 0, 0, 719, 0, 0xb80002831ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #2922 = UCOMISDrr_Int
20611 { 2923, 6, 0, 0, 658, 0|(1ULL<<MCID::MayLoad), 0xb80002021ULL, nullptr, ImplicitList1, OperandInfo171, -1 ,nullptr }, // Inst #2923 = UCOMISSrm
20612 { 2924, 6, 0, 0, 658, 0|(1ULL<<MCID::MayLoad), 0xb80002021ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #2924 = UCOMISSrm_Int
20613 { 2925, 2, 0, 0, 719, 0, 0xb80002031ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr }, // Inst #2925 = UCOMISSrr
20614 { 2926, 2, 0, 0, 719, 0, 0xb80002031ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #2926 = UCOMISSrr_Int
20630 { 2942, 1, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2b8000383eULL, ImplicitList21, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #2942 = UMWAIT
20651 { 2963, 9, 1, 0, 8, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo326, -1 ,nullptr }, // Inst #2963 = VAARG_64
20980 { 3292, 3, 0, 0, 8, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList1, OperandInfo406, -1 ,nullptr }, // Inst #3292 = VASTART_SAVE_XMM_REGS
21227 { 3539, 6, 0, 0, 76, 0|(1ULL<<MCID::MayLoad), 0x1004bf0002821ULL, nullptr, ImplicitList1, OperandInfo473, -1 ,nullptr }, // Inst #3539 = VCOMISDZrm
21228 { 3540, 6, 0, 0, 76, 0|(1ULL<<MCID::MayLoad), 0x1004bf0002821ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr }, // Inst #3540 = VCOMISDZrm_Int
21229 { 3541, 2, 0, 0, 77, 0, 0x1004bf0002831ULL, nullptr, ImplicitList1, OperandInfo474, -1 ,nullptr }, // Inst #3541 = VCOMISDZrr
21230 { 3542, 2, 0, 0, 77, 0, 0x1004bf0002831ULL, nullptr, ImplicitList1, OperandInfo431, -1 ,nullptr }, // Inst #3542 = VCOMISDZrr_Int
21231 { 3543, 2, 0, 0, 77, 0, 0x1104bf8022831ULL, nullptr, ImplicitList1, OperandInfo431, -1 ,nullptr }, // Inst #3543 = VCOMISDZrrb
21232 { 3544, 6, 0, 0, 763, 0|(1ULL<<MCID::MayLoad), 0xbd0002821ULL, nullptr, ImplicitList1, OperandInfo169, -1 ,nullptr }, // Inst #3544 = VCOMISDrm
21233 { 3545, 6, 0, 0, 763, 0|(1ULL<<MCID::MayLoad), 0xbd0002821ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #3545 = VCOMISDrm_Int
21234 { 3546, 2, 0, 0, 720, 0, 0xbd0002831ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr }, // Inst #3546 = VCOMISDrr
21235 { 3547, 2, 0, 0, 720, 0, 0xbd0002831ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #3547 = VCOMISDrr_Int
21236 { 3548, 6, 0, 0, 76, 0|(1ULL<<MCID::MayLoad), 0x800bf0002021ULL, nullptr, ImplicitList1, OperandInfo475, -1 ,nullptr }, // Inst #3548 = VCOMISSZrm
21237 { 3549, 6, 0, 0, 76, 0|(1ULL<<MCID::MayLoad), 0x800bf0002021ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr }, // Inst #3549 = VCOMISSZrm_Int
21238 { 3550, 2, 0, 0, 77, 0, 0x800bf0002031ULL, nullptr, ImplicitList1, OperandInfo476, -1 ,nullptr }, // Inst #3550 = VCOMISSZrr
21239 { 3551, 2, 0, 0, 77, 0, 0x800bf0002031ULL, nullptr, ImplicitList1, OperandInfo431, -1 ,nullptr }, // Inst #3551 = VCOMISSZrr_Int
21240 { 3552, 2, 0, 0, 77, 0, 0x900bf4022031ULL, nullptr, ImplicitList1, OperandInfo431, -1 ,nullptr }, // Inst #3552 = VCOMISSZrrb
21241 { 3553, 6, 0, 0, 763, 0|(1ULL<<MCID::MayLoad), 0xbd0002021ULL, nullptr, ImplicitList1, OperandInfo171, -1 ,nullptr }, // Inst #3553 = VCOMISSrm
21242 { 3554, 6, 0, 0, 763, 0|(1ULL<<MCID::MayLoad), 0xbd0002021ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #3554 = VCOMISSrm_Int
21243 { 3555, 2, 0, 0, 720, 0, 0xbd0002031ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr }, // Inst #3555 = VCOMISSrr
21244 { 3556, 2, 0, 0, 720, 0, 0xbd0002031ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #3556 = VCOMISSrr_Int
31422 { 13734, 6, 0, 0, 544, 0|(1ULL<<MCID::MayLoad), 0x105dc004821ULL, nullptr, ImplicitList1, OperandInfo413, -1 ,nullptr }, // Inst #13734 = VPTESTYrm
31423 { 13735, 2, 0, 0, 545, 0, 0x105dc004831ULL, nullptr, ImplicitList1, OperandInfo501, -1 ,nullptr }, // Inst #13735 = VPTESTYrr
31424 { 13736, 6, 0, 0, 277, 0|(1ULL<<MCID::MayLoad), 0x5dc004821ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #13736 = VPTESTrm
31425 { 13737, 2, 0, 0, 278, 0, 0x5dc004831ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #13737 = VPTESTrr
32611 { 14923, 6, 0, 0, 573, 0|(1ULL<<MCID::MayLoad), 0x103d8004821ULL, nullptr, ImplicitList1, OperandInfo413, -1 ,nullptr }, // Inst #14923 = VTESTPDYrm
32612 { 14924, 2, 0, 0, 574, 0, 0x103d8004831ULL, nullptr, ImplicitList1, OperandInfo501, -1 ,nullptr }, // Inst #14924 = VTESTPDYrr
32613 { 14925, 6, 0, 0, 575, 0|(1ULL<<MCID::MayLoad), 0x3d8004821ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #14925 = VTESTPDrm
32614 { 14926, 2, 0, 0, 576, 0, 0x3d8004831ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #14926 = VTESTPDrr
32615 { 14927, 6, 0, 0, 573, 0|(1ULL<<MCID::MayLoad), 0x10394004821ULL, nullptr, ImplicitList1, OperandInfo413, -1 ,nullptr }, // Inst #14927 = VTESTPSYrm
32616 { 14928, 2, 0, 0, 574, 0, 0x10394004831ULL, nullptr, ImplicitList1, OperandInfo501, -1 ,nullptr }, // Inst #14928 = VTESTPSYrr
32617 { 14929, 6, 0, 0, 575, 0|(1ULL<<MCID::MayLoad), 0x394004821ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #14929 = VTESTPSrm
32618 { 14930, 2, 0, 0, 576, 0, 0x394004831ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #14930 = VTESTPSrr
32619 { 14931, 6, 0, 0, 76, 0|(1ULL<<MCID::MayLoad), 0x1004bb0002821ULL, nullptr, ImplicitList1, OperandInfo473, -1 ,nullptr }, // Inst #14931 = VUCOMISDZrm
32620 { 14932, 6, 0, 0, 76, 0|(1ULL<<MCID::MayLoad), 0x1004bb0002821ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr }, // Inst #14932 = VUCOMISDZrm_Int
32621 { 14933, 2, 0, 0, 77, 0, 0x1004bb0002831ULL, nullptr, ImplicitList1, OperandInfo474, -1 ,nullptr }, // Inst #14933 = VUCOMISDZrr
32622 { 14934, 2, 0, 0, 77, 0, 0x1004bb0002831ULL, nullptr, ImplicitList1, OperandInfo431, -1 ,nullptr }, // Inst #14934 = VUCOMISDZrr_Int
32623 { 14935, 2, 0, 0, 77, 0, 0x1104bb8022831ULL, nullptr, ImplicitList1, OperandInfo431, -1 ,nullptr }, // Inst #14935 = VUCOMISDZrrb
32624 { 14936, 6, 0, 0, 763, 0|(1ULL<<MCID::MayLoad), 0xb90002821ULL, nullptr, ImplicitList1, OperandInfo169, -1 ,nullptr }, // Inst #14936 = VUCOMISDrm
32625 { 14937, 6, 0, 0, 763, 0|(1ULL<<MCID::MayLoad), 0xb90002821ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #14937 = VUCOMISDrm_Int
32626 { 14938, 2, 0, 0, 720, 0, 0xb90002831ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr }, // Inst #14938 = VUCOMISDrr
32627 { 14939, 2, 0, 0, 720, 0, 0xb90002831ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #14939 = VUCOMISDrr_Int
32628 { 14940, 6, 0, 0, 76, 0|(1ULL<<MCID::MayLoad), 0x800bb0002021ULL, nullptr, ImplicitList1, OperandInfo475, -1 ,nullptr }, // Inst #14940 = VUCOMISSZrm
32629 { 14941, 6, 0, 0, 76, 0|(1ULL<<MCID::MayLoad), 0x800bb0002021ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr }, // Inst #14941 = VUCOMISSZrm_Int
32630 { 14942, 2, 0, 0, 77, 0, 0x800bb0002031ULL, nullptr, ImplicitList1, OperandInfo476, -1 ,nullptr }, // Inst #14942 = VUCOMISSZrr
32631 { 14943, 2, 0, 0, 77, 0, 0x800bb0002031ULL, nullptr, ImplicitList1, OperandInfo431, -1 ,nullptr }, // Inst #14943 = VUCOMISSZrr_Int
32632 { 14944, 2, 0, 0, 77, 0, 0x900bb4022031ULL, nullptr, ImplicitList1, OperandInfo431, -1 ,nullptr }, // Inst #14944 = VUCOMISSZrrb
32633 { 14945, 6, 0, 0, 763, 0|(1ULL<<MCID::MayLoad), 0xb90002021ULL, nullptr, ImplicitList1, OperandInfo171, -1 ,nullptr }, // Inst #14945 = VUCOMISSrm
32634 { 14946, 6, 0, 0, 763, 0|(1ULL<<MCID::MayLoad), 0xb90002021ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #14946 = VUCOMISSrm_Int
32635 { 14947, 2, 0, 0, 720, 0, 0xb90002031ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr }, // Inst #14947 = VUCOMISSrr
32636 { 14948, 2, 0, 0, 720, 0, 0xb90002031ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #14948 = VUCOMISSrr_Int
32844 { 15156, 7, 1, 0, 766, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x30400020a1ULL, nullptr, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #15156 = XADD16rm
32845 { 15157, 4, 2, 0, 960, 0, 0x30400020b0ULL, nullptr, ImplicitList1, OperandInfo1009, -1 ,nullptr }, // Inst #15157 = XADD16rr
32846 { 15158, 7, 1, 0, 766, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3040002121ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #15158 = XADD32rm
32847 { 15159, 4, 2, 0, 960, 0, 0x3040002130ULL, nullptr, ImplicitList1, OperandInfo1010, -1 ,nullptr }, // Inst #15159 = XADD32rr
32848 { 15160, 7, 1, 0, 766, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3040012021ULL, nullptr, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #15160 = XADD64rm
32849 { 15161, 4, 2, 0, 960, 0, 0x3040012030ULL, nullptr, ImplicitList1, OperandInfo1011, -1 ,nullptr }, // Inst #15161 = XADD64rr
32850 { 15162, 7, 1, 0, 766, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x3000002021ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #15162 = XADD8rm
32851 { 15163, 4, 2, 0, 960, 0, 0x3000002030ULL, nullptr, ImplicitList1, OperandInfo1012, -1 ,nullptr }, // Inst #15163 = XADD8rr
32876 { 15188, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400800aeULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #15188 = XOR16mi
32877 { 15189, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c00200aeULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #15189 = XOR16mi8
32878 { 15190, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc400000a0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr }, // Inst #15190 = XOR16mr
32879 { 15191, 3, 1, 0, 1, 0, 0x20400800beULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #15191 = XOR16ri
32880 { 15192, 3, 1, 0, 1, 0, 0x20c00200beULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #15192 = XOR16ri8
32881 { 15193, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0xcc00000a1ULL, nullptr, ImplicitList1, OperandInfo78, -1 ,nullptr }, // Inst #15193 = XOR16rm
32882 { 15194, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0xc400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #15194 = XOR16rr
32883 { 15195, 3, 1, 0, 1, 0, 0xcc00000b1ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #15195 = XOR16rr_REV
32885 { 15197, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20400c012eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #15197 = XOR32mi
32886 { 15198, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c002012eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #15198 = XOR32mi8
32887 { 15199, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc40000120ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr }, // Inst #15199 = XOR32mr
32888 { 15200, 3, 1, 0, 1, 0, 0x20400c013eULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #15200 = XOR32ri
32889 { 15201, 3, 1, 0, 1, 0, 0x20c002013eULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #15201 = XOR32ri8
32890 { 15202, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0xcc0000121ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr }, // Inst #15202 = XOR32rm
32891 { 15203, 3, 1, 0, 784, 0|(1ULL<<MCID::Commutable), 0xc40000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #15203 = XOR32rr
32892 { 15204, 3, 1, 0, 1, 0, 0xcc0000131ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #15204 = XOR32rr_REV
32894 { 15206, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x204011002eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #15206 = XOR64mi32
32895 { 15207, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x20c003002eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #15207 = XOR64mi8
32896 { 15208, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc40010020ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr }, // Inst #15208 = XOR64mr
32897 { 15209, 3, 1, 0, 1, 0, 0x204011003eULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #15209 = XOR64ri32
32898 { 15210, 3, 1, 0, 1, 0, 0x20c003003eULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #15210 = XOR64ri8
32899 { 15211, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0xcc0010021ULL, nullptr, ImplicitList1, OperandInfo82, -1 ,nullptr }, // Inst #15211 = XOR64rm
32900 { 15212, 3, 1, 0, 784, 0|(1ULL<<MCID::Commutable), 0xc40010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #15212 = XOR64rr
32901 { 15213, 3, 1, 0, 1, 0, 0xcc0010031ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #15213 = XOR64rr_REV
32903 { 15215, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x200002002eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #15215 = XOR8mi
32904 { 15216, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x208002002eULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr }, // Inst #15216 = XOR8mi8
32905 { 15217, 6, 0, 0, 954, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xc00000020ULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr }, // Inst #15217 = XOR8mr
32906 { 15218, 3, 1, 0, 1, 0, 0x200002003eULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #15218 = XOR8ri
32907 { 15219, 3, 1, 0, 1, 0, 0x208002003eULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #15219 = XOR8ri8
32908 { 15220, 7, 1, 0, 20, 0|(1ULL<<MCID::MayLoad), 0xc80000021ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr }, // Inst #15220 = XOR8rm
32909 { 15221, 3, 1, 0, 1, 0|(1ULL<<MCID::Commutable), 0xc00000030ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #15221 = XOR8rr
32910 { 15222, 3, 1, 0, 1, 0, 0xc80000031ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #15222 = XOR8rr_REV
32932 { 15244, 0, 0, 0, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40002056ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #15244 = XTEST