|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenAsmMatcher.inc 8304 { 897 /* cmovael */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_3, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8310 { 921 /* cmoval */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_7, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8316 { 955 /* cmovbel */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_6, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8322 { 979 /* cmovbl */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_2, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8328 { 1006 /* cmovel */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_4, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8334 { 1040 /* cmovgel */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_13, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8340 { 1064 /* cmovgl */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_15, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8346 { 1098 /* cmovlel */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_14, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8352 { 1122 /* cmovll */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_12, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8358 { 1150 /* cmovnel */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_5, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8364 { 1181 /* cmovnol */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_1, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8370 { 1212 /* cmovnpl */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_11, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8376 { 1243 /* cmovnsl */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_9, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8382 { 1273 /* cmovol */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8388 { 1300 /* cmovpl */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_10, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8394 { 1327 /* cmovsl */, X86::CMOV32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0__imm_95_8, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22896 { 884 /* cmova */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_7, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22902 { 890 /* cmovae */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_3, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22908 { 942 /* cmovb */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_2, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22914 { 948 /* cmovbe */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_6, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22920 { 1000 /* cmove */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_4, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22926 { 1027 /* cmovg */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_15, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22932 { 1033 /* cmovge */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_13, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22938 { 1085 /* cmovl */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_12, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22944 { 1091 /* cmovle */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_14, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22950 { 1143 /* cmovne */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_5, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22956 { 1174 /* cmovno */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_1, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22962 { 1205 /* cmovnp */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_11, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22968 { 1236 /* cmovns */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_9, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22974 { 1267 /* cmovo */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22980 { 1294 /* cmovp */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_10, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22986 { 1321 /* cmovs */, X86::CMOV32rr, Convert__Reg1_0__Tie0_1_1__Reg1_1__imm_95_8, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
gen/lib/Target/X86/X86GenDAGISel.inc33505 /* 69640*/ OPC_MorphNodeTo1, TARGET_VAL(X86::CMOV32rr), 0|OPFL_GlueInput,
lib/Target/X86/X86ISelDAGToDAG.cpp 2647 else if (Opc == X86::CMOV16rr || Opc == X86::CMOV32rr ||
lib/Target/X86/X86InstrFoldTables.cpp 1242 { X86::CMOV32rr, X86::CMOV32rm, 0 },
lib/Target/X86/X86InstrInfo.cpp 1805 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr: {
2207 case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2306 case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp 253 const unsigned Opcode = X86::CMOV32rr;