reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/X86/X86GenAsmMatcher.inc

 8019   { 66 /* addl */, X86::ADD32ri, Convert__Reg1_1__Tie0_2_2__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR32 }, },
22613   { 57 /* add */, X86::ADD32ri, Convert__Reg1_0__Tie0_1_1__Imm1_1, AMFBS_None, { MCK_GR32, MCK_Imm }, },

gen/lib/Target/X86/X86GenDAGISel.inc

39315 /* 82330*/          OPC_MorphNodeTo2, TARGET_VAL(X86::ADD32ri), 0,
39358 /* 82411*/          OPC_MorphNodeTo2, TARGET_VAL(X86::ADD32ri), 0,
42911 /* 89763*/              OPC_MorphNodeTo2, TARGET_VAL(X86::ADD32ri), 0,

gen/lib/Target/X86/X86GenFastISel.inc

13635   return fastEmitInst_ri(X86::ADD32ri, &X86::GR32RegClass, Op0, Op0IsKill, imm1);

gen/lib/Target/X86/X86GenGlobalISel.inc

 1065         GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri,

lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

  195   case X86::ADD32ri8: return X86::ADD32ri;

lib/Target/X86/X86FixupLEAs.cpp

  159   case X86::ADD32ri:
  334     return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;

lib/Target/X86/X86FrameLowering.cpp

  115     return X86::ADD32ri;
  422        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&

lib/Target/X86/X86ISelLowering.cpp

29428     BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
30118     BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)

lib/Target/X86/X86InstrFoldTables.cpp

   62   { X86::ADD32ri,     X86::ADD32mi,    0 },

lib/Target/X86/X86InstrInfo.cpp

 1086   case X86::ADD32ri:
 3426   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
 4850   if (MI.getOpcode() == X86::ADD32ri &&
 7817           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)

lib/Target/X86/X86MCInstLower.cpp

  821   case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
  838     case X86::ADD32ri:    NewOpc = X86::ADD32i32;  break;
 2000   case X86::ADD32ri: {
 2026     EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)

lib/Target/X86/X86MacroFusion.cpp

  100   case X86::ADD32ri:

lib/Target/X86/X86SpeculativeLoadHardening.cpp

 1315   case X86::ADD32rr:  case X86::ADD32ri:   case X86::ADD32ri8: