|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenAsmMatcher.inc10916 { 8227 /* vblendvpd */, X86::VBLENDVPDrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
10918 { 8227 /* vblendvpd */, X86::VBLENDVPDYrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
10920 { 8237 /* vblendvps */, X86::VBLENDVPSrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
10922 { 8237 /* vblendvps */, X86::VBLENDVPSYrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
12956 { 9935 /* vfmaddpd */, X86::VFMADDPD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
12958 { 9935 /* vfmaddpd */, X86::VFMADDPD4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
12962 { 9944 /* vfmaddps */, X86::VFMADDPS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
12964 { 9944 /* vfmaddps */, X86::VFMADDPS4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
12968 { 9953 /* vfmaddsd */, X86::VFMADDSD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
12971 { 9962 /* vfmaddss */, X86::VFMADDSS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13178 { 10061 /* vfmaddsubpd */, X86::VFMADDSUBPD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13180 { 10061 /* vfmaddsubpd */, X86::VFMADDSUBPD4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
13184 { 10073 /* vfmaddsubps */, X86::VFMADDSUBPS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13186 { 10073 /* vfmaddsubps */, X86::VFMADDSUBPS4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
13664 { 10319 /* vfmsubaddpd */, X86::VFMSUBADDPD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13666 { 10319 /* vfmsubaddpd */, X86::VFMSUBADDPD4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
13670 { 10331 /* vfmsubaddps */, X86::VFMSUBADDPS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13672 { 10331 /* vfmsubaddps */, X86::VFMSUBADDPS4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
13676 { 10343 /* vfmsubpd */, X86::VFMSUBPD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13678 { 10343 /* vfmsubpd */, X86::VFMSUBPD4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
13682 { 10352 /* vfmsubps */, X86::VFMSUBPS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13684 { 10352 /* vfmsubps */, X86::VFMSUBPS4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
13688 { 10361 /* vfmsubsd */, X86::VFMSUBSD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13691 { 10370 /* vfmsubss */, X86::VFMSUBSS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13964 { 10535 /* vfnmaddpd */, X86::VFNMADDPD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13966 { 10535 /* vfnmaddpd */, X86::VFNMADDPD4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
13970 { 10545 /* vfnmaddps */, X86::VFNMADDPS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13972 { 10545 /* vfnmaddps */, X86::VFNMADDPS4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
13976 { 10555 /* vfnmaddsd */, X86::VFNMADDSD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
13979 { 10565 /* vfnmaddss */, X86::VFNMADDSS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
14252 { 10731 /* vfnmsubpd */, X86::VFNMSUBPD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
14254 { 10731 /* vfnmsubpd */, X86::VFNMSUBPD4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
14258 { 10741 /* vfnmsubps */, X86::VFNMSUBPS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
14260 { 10741 /* vfnmsubps */, X86::VFNMSUBPS4Yrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
14264 { 10751 /* vfnmsubsd */, X86::VFNMSUBSD4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
14267 { 10761 /* vfnmsubss */, X86::VFNMSUBSS4rr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
16331 { 12394 /* vpblendvb */, X86::VPBLENDVBrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
16333 { 12394 /* vpblendvb */, X86::VPBLENDVBYrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
16519 { 12564 /* vpcmov */, X86::VPCMOVrrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
16521 { 12564 /* vpcmov */, X86::VPCMOVYrrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256, MCK_VR256 }, },
17857 { 13506 /* vpmacsdd */, X86::VPMACSDDrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17859 { 13515 /* vpmacsdqh */, X86::VPMACSDQHrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17861 { 13525 /* vpmacsdql */, X86::VPMACSDQLrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17863 { 13535 /* vpmacssdd */, X86::VPMACSSDDrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17865 { 13545 /* vpmacssdqh */, X86::VPMACSSDQHrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17867 { 13556 /* vpmacssdql */, X86::VPMACSSDQLrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17869 { 13567 /* vpmacsswd */, X86::VPMACSSWDrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17871 { 13577 /* vpmacssww */, X86::VPMACSSWWrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17873 { 13587 /* vpmacswd */, X86::VPMACSWDrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17875 { 13596 /* vpmacsww */, X86::VPMACSWWrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17877 { 13605 /* vpmadcsswd */, X86::VPMADCSSWDrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
17879 { 13616 /* vpmadcswd */, X86::VPMADCSWDrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },
19338 { 14320 /* vpperm */, X86::VPPERMrrr, Convert__Reg1_3__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32, MCK_FR32 }, },