|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenAsmMatcher.inc12443 { 9526 /* vdpbf16ps */, X86::VDPBF16PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12444 { 9526 /* vdpbf16ps */, X86::VDPBF16PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12445 { 9526 /* vdpbf16ps */, X86::VDPBF16PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
12686 { 9791 /* vfmadd132pd */, X86::VFMADD132PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12687 { 9791 /* vfmadd132pd */, X86::VFMADD132PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
12688 { 9791 /* vfmadd132pd */, X86::VFMADD132PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12689 { 9791 /* vfmadd132pd */, X86::VFMADD132PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12690 { 9791 /* vfmadd132pd */, X86::VFMADD132PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
12720 { 9803 /* vfmadd132ps */, X86::VFMADD132PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12721 { 9803 /* vfmadd132ps */, X86::VFMADD132PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
12722 { 9803 /* vfmadd132ps */, X86::VFMADD132PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12723 { 9803 /* vfmadd132ps */, X86::VFMADD132PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12724 { 9803 /* vfmadd132ps */, X86::VFMADD132PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
12754 { 9815 /* vfmadd132sd */, X86::VFMADD132SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12755 { 9815 /* vfmadd132sd */, X86::VFMADD132SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12765 { 9827 /* vfmadd132ss */, X86::VFMADD132SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12766 { 9827 /* vfmadd132ss */, X86::VFMADD132SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12776 { 9839 /* vfmadd213pd */, X86::VFMADD213PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12777 { 9839 /* vfmadd213pd */, X86::VFMADD213PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
12778 { 9839 /* vfmadd213pd */, X86::VFMADD213PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12779 { 9839 /* vfmadd213pd */, X86::VFMADD213PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12780 { 9839 /* vfmadd213pd */, X86::VFMADD213PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
12810 { 9851 /* vfmadd213ps */, X86::VFMADD213PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12811 { 9851 /* vfmadd213ps */, X86::VFMADD213PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
12812 { 9851 /* vfmadd213ps */, X86::VFMADD213PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12813 { 9851 /* vfmadd213ps */, X86::VFMADD213PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12814 { 9851 /* vfmadd213ps */, X86::VFMADD213PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
12844 { 9863 /* vfmadd213sd */, X86::VFMADD213SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12845 { 9863 /* vfmadd213sd */, X86::VFMADD213SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12855 { 9875 /* vfmadd213ss */, X86::VFMADD213SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12856 { 9875 /* vfmadd213ss */, X86::VFMADD213SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12866 { 9887 /* vfmadd231pd */, X86::VFMADD231PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12867 { 9887 /* vfmadd231pd */, X86::VFMADD231PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
12868 { 9887 /* vfmadd231pd */, X86::VFMADD231PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12869 { 9887 /* vfmadd231pd */, X86::VFMADD231PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12870 { 9887 /* vfmadd231pd */, X86::VFMADD231PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
12900 { 9899 /* vfmadd231ps */, X86::VFMADD231PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12901 { 9899 /* vfmadd231ps */, X86::VFMADD231PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
12902 { 9899 /* vfmadd231ps */, X86::VFMADD231PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12903 { 9899 /* vfmadd231ps */, X86::VFMADD231PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12904 { 9899 /* vfmadd231ps */, X86::VFMADD231PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
12934 { 9911 /* vfmadd231sd */, X86::VFMADD231SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12935 { 9911 /* vfmadd231sd */, X86::VFMADD231SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12945 { 9923 /* vfmadd231ss */, X86::VFMADD231SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12946 { 9923 /* vfmadd231ss */, X86::VFMADD231SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12974 { 9971 /* vfmaddsub132pd */, X86::VFMADDSUB132PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12975 { 9971 /* vfmaddsub132pd */, X86::VFMADDSUB132PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
12976 { 9971 /* vfmaddsub132pd */, X86::VFMADDSUB132PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12977 { 9971 /* vfmaddsub132pd */, X86::VFMADDSUB132PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12978 { 9971 /* vfmaddsub132pd */, X86::VFMADDSUB132PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13008 { 9986 /* vfmaddsub132ps */, X86::VFMADDSUB132PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13009 { 9986 /* vfmaddsub132ps */, X86::VFMADDSUB132PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13010 { 9986 /* vfmaddsub132ps */, X86::VFMADDSUB132PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13011 { 9986 /* vfmaddsub132ps */, X86::VFMADDSUB132PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13012 { 9986 /* vfmaddsub132ps */, X86::VFMADDSUB132PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13042 { 10001 /* vfmaddsub213pd */, X86::VFMADDSUB213PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13043 { 10001 /* vfmaddsub213pd */, X86::VFMADDSUB213PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13044 { 10001 /* vfmaddsub213pd */, X86::VFMADDSUB213PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13045 { 10001 /* vfmaddsub213pd */, X86::VFMADDSUB213PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13046 { 10001 /* vfmaddsub213pd */, X86::VFMADDSUB213PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13076 { 10016 /* vfmaddsub213ps */, X86::VFMADDSUB213PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13077 { 10016 /* vfmaddsub213ps */, X86::VFMADDSUB213PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13078 { 10016 /* vfmaddsub213ps */, X86::VFMADDSUB213PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13079 { 10016 /* vfmaddsub213ps */, X86::VFMADDSUB213PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13080 { 10016 /* vfmaddsub213ps */, X86::VFMADDSUB213PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13110 { 10031 /* vfmaddsub231pd */, X86::VFMADDSUB231PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13111 { 10031 /* vfmaddsub231pd */, X86::VFMADDSUB231PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13112 { 10031 /* vfmaddsub231pd */, X86::VFMADDSUB231PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13113 { 10031 /* vfmaddsub231pd */, X86::VFMADDSUB231PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13114 { 10031 /* vfmaddsub231pd */, X86::VFMADDSUB231PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13144 { 10046 /* vfmaddsub231ps */, X86::VFMADDSUB231PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13145 { 10046 /* vfmaddsub231ps */, X86::VFMADDSUB231PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13146 { 10046 /* vfmaddsub231ps */, X86::VFMADDSUB231PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13147 { 10046 /* vfmaddsub231ps */, X86::VFMADDSUB231PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13148 { 10046 /* vfmaddsub231ps */, X86::VFMADDSUB231PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13190 { 10085 /* vfmsub132pd */, X86::VFMSUB132PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13191 { 10085 /* vfmsub132pd */, X86::VFMSUB132PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13192 { 10085 /* vfmsub132pd */, X86::VFMSUB132PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13193 { 10085 /* vfmsub132pd */, X86::VFMSUB132PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13194 { 10085 /* vfmsub132pd */, X86::VFMSUB132PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13224 { 10097 /* vfmsub132ps */, X86::VFMSUB132PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13225 { 10097 /* vfmsub132ps */, X86::VFMSUB132PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13226 { 10097 /* vfmsub132ps */, X86::VFMSUB132PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13227 { 10097 /* vfmsub132ps */, X86::VFMSUB132PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13228 { 10097 /* vfmsub132ps */, X86::VFMSUB132PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13258 { 10109 /* vfmsub132sd */, X86::VFMSUB132SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13259 { 10109 /* vfmsub132sd */, X86::VFMSUB132SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13269 { 10121 /* vfmsub132ss */, X86::VFMSUB132SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13270 { 10121 /* vfmsub132ss */, X86::VFMSUB132SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13280 { 10133 /* vfmsub213pd */, X86::VFMSUB213PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13281 { 10133 /* vfmsub213pd */, X86::VFMSUB213PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13282 { 10133 /* vfmsub213pd */, X86::VFMSUB213PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13283 { 10133 /* vfmsub213pd */, X86::VFMSUB213PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13284 { 10133 /* vfmsub213pd */, X86::VFMSUB213PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13314 { 10145 /* vfmsub213ps */, X86::VFMSUB213PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13315 { 10145 /* vfmsub213ps */, X86::VFMSUB213PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13316 { 10145 /* vfmsub213ps */, X86::VFMSUB213PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13317 { 10145 /* vfmsub213ps */, X86::VFMSUB213PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13318 { 10145 /* vfmsub213ps */, X86::VFMSUB213PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13348 { 10157 /* vfmsub213sd */, X86::VFMSUB213SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13349 { 10157 /* vfmsub213sd */, X86::VFMSUB213SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13359 { 10169 /* vfmsub213ss */, X86::VFMSUB213SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13360 { 10169 /* vfmsub213ss */, X86::VFMSUB213SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13370 { 10181 /* vfmsub231pd */, X86::VFMSUB231PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13371 { 10181 /* vfmsub231pd */, X86::VFMSUB231PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13372 { 10181 /* vfmsub231pd */, X86::VFMSUB231PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13373 { 10181 /* vfmsub231pd */, X86::VFMSUB231PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13374 { 10181 /* vfmsub231pd */, X86::VFMSUB231PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13404 { 10193 /* vfmsub231ps */, X86::VFMSUB231PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13405 { 10193 /* vfmsub231ps */, X86::VFMSUB231PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13406 { 10193 /* vfmsub231ps */, X86::VFMSUB231PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13407 { 10193 /* vfmsub231ps */, X86::VFMSUB231PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13408 { 10193 /* vfmsub231ps */, X86::VFMSUB231PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13438 { 10205 /* vfmsub231sd */, X86::VFMSUB231SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13439 { 10205 /* vfmsub231sd */, X86::VFMSUB231SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13449 { 10217 /* vfmsub231ss */, X86::VFMSUB231SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13450 { 10217 /* vfmsub231ss */, X86::VFMSUB231SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13460 { 10229 /* vfmsubadd132pd */, X86::VFMSUBADD132PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13461 { 10229 /* vfmsubadd132pd */, X86::VFMSUBADD132PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13462 { 10229 /* vfmsubadd132pd */, X86::VFMSUBADD132PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13463 { 10229 /* vfmsubadd132pd */, X86::VFMSUBADD132PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13464 { 10229 /* vfmsubadd132pd */, X86::VFMSUBADD132PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13494 { 10244 /* vfmsubadd132ps */, X86::VFMSUBADD132PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13495 { 10244 /* vfmsubadd132ps */, X86::VFMSUBADD132PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13496 { 10244 /* vfmsubadd132ps */, X86::VFMSUBADD132PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13497 { 10244 /* vfmsubadd132ps */, X86::VFMSUBADD132PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13498 { 10244 /* vfmsubadd132ps */, X86::VFMSUBADD132PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13528 { 10259 /* vfmsubadd213pd */, X86::VFMSUBADD213PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13529 { 10259 /* vfmsubadd213pd */, X86::VFMSUBADD213PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13530 { 10259 /* vfmsubadd213pd */, X86::VFMSUBADD213PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13531 { 10259 /* vfmsubadd213pd */, X86::VFMSUBADD213PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13532 { 10259 /* vfmsubadd213pd */, X86::VFMSUBADD213PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13562 { 10274 /* vfmsubadd213ps */, X86::VFMSUBADD213PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13563 { 10274 /* vfmsubadd213ps */, X86::VFMSUBADD213PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13564 { 10274 /* vfmsubadd213ps */, X86::VFMSUBADD213PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13565 { 10274 /* vfmsubadd213ps */, X86::VFMSUBADD213PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13566 { 10274 /* vfmsubadd213ps */, X86::VFMSUBADD213PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13596 { 10289 /* vfmsubadd231pd */, X86::VFMSUBADD231PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13597 { 10289 /* vfmsubadd231pd */, X86::VFMSUBADD231PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13598 { 10289 /* vfmsubadd231pd */, X86::VFMSUBADD231PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13599 { 10289 /* vfmsubadd231pd */, X86::VFMSUBADD231PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13600 { 10289 /* vfmsubadd231pd */, X86::VFMSUBADD231PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13630 { 10304 /* vfmsubadd231ps */, X86::VFMSUBADD231PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13631 { 10304 /* vfmsubadd231ps */, X86::VFMSUBADD231PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13632 { 10304 /* vfmsubadd231ps */, X86::VFMSUBADD231PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13633 { 10304 /* vfmsubadd231ps */, X86::VFMSUBADD231PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13634 { 10304 /* vfmsubadd231ps */, X86::VFMSUBADD231PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13694 { 10379 /* vfnmadd132pd */, X86::VFNMADD132PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13695 { 10379 /* vfnmadd132pd */, X86::VFNMADD132PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13696 { 10379 /* vfnmadd132pd */, X86::VFNMADD132PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13697 { 10379 /* vfnmadd132pd */, X86::VFNMADD132PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13698 { 10379 /* vfnmadd132pd */, X86::VFNMADD132PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13728 { 10392 /* vfnmadd132ps */, X86::VFNMADD132PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13729 { 10392 /* vfnmadd132ps */, X86::VFNMADD132PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13730 { 10392 /* vfnmadd132ps */, X86::VFNMADD132PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13731 { 10392 /* vfnmadd132ps */, X86::VFNMADD132PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13732 { 10392 /* vfnmadd132ps */, X86::VFNMADD132PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13762 { 10405 /* vfnmadd132sd */, X86::VFNMADD132SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13763 { 10405 /* vfnmadd132sd */, X86::VFNMADD132SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13773 { 10418 /* vfnmadd132ss */, X86::VFNMADD132SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13774 { 10418 /* vfnmadd132ss */, X86::VFNMADD132SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13784 { 10431 /* vfnmadd213pd */, X86::VFNMADD213PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13785 { 10431 /* vfnmadd213pd */, X86::VFNMADD213PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13786 { 10431 /* vfnmadd213pd */, X86::VFNMADD213PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13787 { 10431 /* vfnmadd213pd */, X86::VFNMADD213PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13788 { 10431 /* vfnmadd213pd */, X86::VFNMADD213PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13818 { 10444 /* vfnmadd213ps */, X86::VFNMADD213PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13819 { 10444 /* vfnmadd213ps */, X86::VFNMADD213PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13820 { 10444 /* vfnmadd213ps */, X86::VFNMADD213PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13821 { 10444 /* vfnmadd213ps */, X86::VFNMADD213PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13822 { 10444 /* vfnmadd213ps */, X86::VFNMADD213PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13852 { 10457 /* vfnmadd213sd */, X86::VFNMADD213SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13853 { 10457 /* vfnmadd213sd */, X86::VFNMADD213SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13863 { 10470 /* vfnmadd213ss */, X86::VFNMADD213SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13864 { 10470 /* vfnmadd213ss */, X86::VFNMADD213SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13874 { 10483 /* vfnmadd231pd */, X86::VFNMADD231PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13875 { 10483 /* vfnmadd231pd */, X86::VFNMADD231PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13876 { 10483 /* vfnmadd231pd */, X86::VFNMADD231PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13877 { 10483 /* vfnmadd231pd */, X86::VFNMADD231PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13878 { 10483 /* vfnmadd231pd */, X86::VFNMADD231PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13908 { 10496 /* vfnmadd231ps */, X86::VFNMADD231PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13909 { 10496 /* vfnmadd231ps */, X86::VFNMADD231PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13910 { 10496 /* vfnmadd231ps */, X86::VFNMADD231PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13911 { 10496 /* vfnmadd231ps */, X86::VFNMADD231PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13912 { 10496 /* vfnmadd231ps */, X86::VFNMADD231PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
13942 { 10509 /* vfnmadd231sd */, X86::VFNMADD231SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13943 { 10509 /* vfnmadd231sd */, X86::VFNMADD231SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13953 { 10522 /* vfnmadd231ss */, X86::VFNMADD231SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13954 { 10522 /* vfnmadd231ss */, X86::VFNMADD231SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13982 { 10575 /* vfnmsub132pd */, X86::VFNMSUB132PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
13983 { 10575 /* vfnmsub132pd */, X86::VFNMSUB132PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
13984 { 10575 /* vfnmsub132pd */, X86::VFNMSUB132PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
13985 { 10575 /* vfnmsub132pd */, X86::VFNMSUB132PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
13986 { 10575 /* vfnmsub132pd */, X86::VFNMSUB132PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14016 { 10588 /* vfnmsub132ps */, X86::VFNMSUB132PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14017 { 10588 /* vfnmsub132ps */, X86::VFNMSUB132PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14018 { 10588 /* vfnmsub132ps */, X86::VFNMSUB132PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14019 { 10588 /* vfnmsub132ps */, X86::VFNMSUB132PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14020 { 10588 /* vfnmsub132ps */, X86::VFNMSUB132PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14050 { 10601 /* vfnmsub132sd */, X86::VFNMSUB132SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14051 { 10601 /* vfnmsub132sd */, X86::VFNMSUB132SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14061 { 10614 /* vfnmsub132ss */, X86::VFNMSUB132SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14062 { 10614 /* vfnmsub132ss */, X86::VFNMSUB132SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14072 { 10627 /* vfnmsub213pd */, X86::VFNMSUB213PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14073 { 10627 /* vfnmsub213pd */, X86::VFNMSUB213PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14074 { 10627 /* vfnmsub213pd */, X86::VFNMSUB213PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14075 { 10627 /* vfnmsub213pd */, X86::VFNMSUB213PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14076 { 10627 /* vfnmsub213pd */, X86::VFNMSUB213PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14106 { 10640 /* vfnmsub213ps */, X86::VFNMSUB213PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14107 { 10640 /* vfnmsub213ps */, X86::VFNMSUB213PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14108 { 10640 /* vfnmsub213ps */, X86::VFNMSUB213PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14109 { 10640 /* vfnmsub213ps */, X86::VFNMSUB213PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14110 { 10640 /* vfnmsub213ps */, X86::VFNMSUB213PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14140 { 10653 /* vfnmsub213sd */, X86::VFNMSUB213SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14141 { 10653 /* vfnmsub213sd */, X86::VFNMSUB213SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14151 { 10666 /* vfnmsub213ss */, X86::VFNMSUB213SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14152 { 10666 /* vfnmsub213ss */, X86::VFNMSUB213SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14162 { 10679 /* vfnmsub231pd */, X86::VFNMSUB231PDr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14163 { 10679 /* vfnmsub231pd */, X86::VFNMSUB231PDYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14164 { 10679 /* vfnmsub231pd */, X86::VFNMSUB231PDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14165 { 10679 /* vfnmsub231pd */, X86::VFNMSUB231PDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14166 { 10679 /* vfnmsub231pd */, X86::VFNMSUB231PDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14196 { 10692 /* vfnmsub231ps */, X86::VFNMSUB231PSr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14197 { 10692 /* vfnmsub231ps */, X86::VFNMSUB231PSYr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14198 { 10692 /* vfnmsub231ps */, X86::VFNMSUB231PSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14199 { 10692 /* vfnmsub231ps */, X86::VFNMSUB231PSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14200 { 10692 /* vfnmsub231ps */, X86::VFNMSUB231PSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14230 { 10705 /* vfnmsub231sd */, X86::VFNMSUB231SDr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14231 { 10705 /* vfnmsub231sd */, X86::VFNMSUB231SDZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14241 { 10718 /* vfnmsub231ss */, X86::VFNMSUB231SSr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14242 { 10718 /* vfnmsub231ss */, X86::VFNMSUB231SSZr_Int, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16935 { 12879 /* vpdpbusd */, X86::VPDPBUSDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16936 { 12879 /* vpdpbusd */, X86::VPDPBUSDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16937 { 12879 /* vpdpbusd */, X86::VPDPBUSDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16962 { 12888 /* vpdpbusds */, X86::VPDPBUSDSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16963 { 12888 /* vpdpbusds */, X86::VPDPBUSDSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16964 { 12888 /* vpdpbusds */, X86::VPDPBUSDSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16989 { 12898 /* vpdpwssd */, X86::VPDPWSSDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16990 { 12898 /* vpdpwssd */, X86::VPDPWSSDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16991 { 12898 /* vpdpwssd */, X86::VPDPWSSDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17016 { 12907 /* vpdpwssds */, X86::VPDPWSSDSZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17017 { 12907 /* vpdpwssds */, X86::VPDPWSSDSZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17018 { 12907 /* vpdpwssds */, X86::VPDPWSSDSZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17085 { 12953 /* vpermi2b */, X86::VPERMI2B128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17086 { 12953 /* vpermi2b */, X86::VPERMI2B256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17087 { 12953 /* vpermi2b */, X86::VPERMI2Brr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17103 { 12962 /* vpermi2d */, X86::VPERMI2D128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17104 { 12962 /* vpermi2d */, X86::VPERMI2D256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17105 { 12962 /* vpermi2d */, X86::VPERMI2Drr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17130 { 12971 /* vpermi2pd */, X86::VPERMI2PD128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17131 { 12971 /* vpermi2pd */, X86::VPERMI2PD256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17132 { 12971 /* vpermi2pd */, X86::VPERMI2PDrr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17157 { 12981 /* vpermi2ps */, X86::VPERMI2PS128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17158 { 12981 /* vpermi2ps */, X86::VPERMI2PS256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17159 { 12981 /* vpermi2ps */, X86::VPERMI2PSrr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17184 { 12991 /* vpermi2q */, X86::VPERMI2Q128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17185 { 12991 /* vpermi2q */, X86::VPERMI2Q256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17186 { 12991 /* vpermi2q */, X86::VPERMI2Qrr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17211 { 13000 /* vpermi2w */, X86::VPERMI2W128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17212 { 13000 /* vpermi2w */, X86::VPERMI2W256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17213 { 13000 /* vpermi2w */, X86::VPERMI2Wrr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17461 { 13074 /* vpermt2b */, X86::VPERMT2B128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17462 { 13074 /* vpermt2b */, X86::VPERMT2B256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17463 { 13074 /* vpermt2b */, X86::VPERMT2Brr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17479 { 13083 /* vpermt2d */, X86::VPERMT2D128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17480 { 13083 /* vpermt2d */, X86::VPERMT2D256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17481 { 13083 /* vpermt2d */, X86::VPERMT2Drr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17506 { 13092 /* vpermt2pd */, X86::VPERMT2PD128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17507 { 13092 /* vpermt2pd */, X86::VPERMT2PD256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17508 { 13092 /* vpermt2pd */, X86::VPERMT2PDrr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17533 { 13102 /* vpermt2ps */, X86::VPERMT2PS128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17534 { 13102 /* vpermt2ps */, X86::VPERMT2PS256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17535 { 13102 /* vpermt2ps */, X86::VPERMT2PSrr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17560 { 13112 /* vpermt2q */, X86::VPERMT2Q128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17561 { 13112 /* vpermt2q */, X86::VPERMT2Q256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17562 { 13112 /* vpermt2q */, X86::VPERMT2Qrr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17587 { 13121 /* vpermt2w */, X86::VPERMT2W128rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17588 { 13121 /* vpermt2w */, X86::VPERMT2W256rr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17589 { 13121 /* vpermt2w */, X86::VPERMT2Wrr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17881 { 13626 /* vpmadd52huq */, X86::VPMADD52HUQZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17882 { 13626 /* vpmadd52huq */, X86::VPMADD52HUQZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17883 { 13626 /* vpmadd52huq */, X86::VPMADD52HUQZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17908 { 13638 /* vpmadd52luq */, X86::VPMADD52LUQZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17909 { 13638 /* vpmadd52luq */, X86::VPMADD52LUQZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17910 { 13638 /* vpmadd52luq */, X86::VPMADD52LUQZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19671 { 14529 /* vpshldvd */, X86::VPSHLDVDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19672 { 14529 /* vpshldvd */, X86::VPSHLDVDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19673 { 14529 /* vpshldvd */, X86::VPSHLDVDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19698 { 14538 /* vpshldvq */, X86::VPSHLDVQZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19699 { 14538 /* vpshldvq */, X86::VPSHLDVQZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19700 { 14538 /* vpshldvq */, X86::VPSHLDVQZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19725 { 14547 /* vpshldvw */, X86::VPSHLDVWZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19726 { 14547 /* vpshldvw */, X86::VPSHLDVWZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19727 { 14547 /* vpshldvw */, X86::VPSHLDVWZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19821 { 14594 /* vpshrdvd */, X86::VPSHRDVDZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19822 { 14594 /* vpshrdvd */, X86::VPSHRDVDZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19823 { 14594 /* vpshrdvd */, X86::VPSHRDVDZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19848 { 14603 /* vpshrdvq */, X86::VPSHRDVQZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19849 { 14603 /* vpshrdvq */, X86::VPSHRDVQZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19850 { 14603 /* vpshrdvq */, X86::VPSHRDVQZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19875 { 14612 /* vpshrdvw */, X86::VPSHRDVWZ128r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19876 { 14612 /* vpshrdvw */, X86::VPSHRDVWZ256r, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19877 { 14612 /* vpshrdvw */, X86::VPSHRDVWZr, Convert__Reg1_2__Tie0_1_1__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },