reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 8083   { 218 /* andnl */, X86::ANDN32rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
 8089   { 238 /* andnq */, X86::ANDN64rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
 8115   { 277 /* bextrl */, X86::BEXTR32rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
 8119   { 284 /* bextrq */, X86::BEXTR64rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
 8264   { 717 /* bzhil */, X86::BZHI32rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
 8266   { 723 /* bzhiq */, X86::BZHI64rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
 8952   { 3437 /* kaddb */, X86::KADDBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8953   { 3443 /* kaddd */, X86::KADDDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8954   { 3449 /* kaddq */, X86::KADDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8955   { 3455 /* kaddw */, X86::KADDWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8956   { 3461 /* kandb */, X86::KANDBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8957   { 3467 /* kandd */, X86::KANDDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8958   { 3473 /* kandnb */, X86::KANDNBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8959   { 3480 /* kandnd */, X86::KANDNDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8960   { 3487 /* kandnq */, X86::KANDNQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8961   { 3494 /* kandnw */, X86::KANDNWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8962   { 3501 /* kandq */, X86::KANDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8963   { 3507 /* kandw */, X86::KANDWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8988   { 3561 /* korb */, X86::KORBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8989   { 3566 /* kord */, X86::KORDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8990   { 3571 /* korq */, X86::KORQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 8995   { 3612 /* korw */, X86::KORWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9008   { 3717 /* kunpckbw */, X86::KUNPCKBWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9009   { 3726 /* kunpckdq */, X86::KUNPCKDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9010   { 3735 /* kunpckwd */, X86::KUNPCKWDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9011   { 3744 /* kxnorb */, X86::KXNORBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9012   { 3751 /* kxnord */, X86::KXNORDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9013   { 3758 /* kxnorq */, X86::KXNORQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9014   { 3765 /* kxnorw */, X86::KXNORWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9015   { 3772 /* kxorb */, X86::KXORBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9016   { 3778 /* kxord */, X86::KXORDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9017   { 3784 /* kxorq */, X86::KXORQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9018   { 3790 /* kxorw */, X86::KXORWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
 9373   { 4973 /* mulxl */, X86::MULX32rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
 9375   { 4979 /* mulxq */, X86::MULX64rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
 9592   { 5491 /* pdepl */, X86::PDEP32rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
 9594   { 5497 /* pdepq */, X86::PDEP64rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
 9596   { 5508 /* pextl */, X86::PEXT32rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
 9598   { 5514 /* pextq */, X86::PEXT64rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
10172   { 7050 /* sarxl */, X86::SARX32rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
10174   { 7056 /* sarxq */, X86::SARX64rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
10317   { 7390 /* shlxl */, X86::SHLX32rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
10319   { 7396 /* shlxq */, X86::SHLX64rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
10363   { 7454 /* shrxl */, X86::SHRX32rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
10365   { 7460 /* shrxq */, X86::SHRX64rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
10534   { 8030 /* vaddpd */, X86::VADDPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10535   { 8030 /* vaddpd */, X86::VADDPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10536   { 8030 /* vaddpd */, X86::VADDPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10537   { 8030 /* vaddpd */, X86::VADDPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10538   { 8030 /* vaddpd */, X86::VADDPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10568   { 8037 /* vaddps */, X86::VADDPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10569   { 8037 /* vaddps */, X86::VADDPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10570   { 8037 /* vaddps */, X86::VADDPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10571   { 8037 /* vaddps */, X86::VADDPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10572   { 8037 /* vaddps */, X86::VADDPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10602   { 8044 /* vaddsd */, X86::VADDSDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10603   { 8044 /* vaddsd */, X86::VADDSDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10613   { 8051 /* vaddss */, X86::VADDSSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10614   { 8051 /* vaddss */, X86::VADDSSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10624   { 8058 /* vaddsubpd */, X86::VADDSUBPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10625   { 8058 /* vaddsubpd */, X86::VADDSUBPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10628   { 8068 /* vaddsubps */, X86::VADDSUBPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10629   { 8068 /* vaddsubps */, X86::VADDSUBPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10632   { 8078 /* vaesdec */, X86::VAESDECrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10633   { 8078 /* vaesdec */, X86::VAESDECYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10634   { 8078 /* vaesdec */, X86::VAESDECZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10635   { 8078 /* vaesdec */, X86::VAESDECZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10636   { 8078 /* vaesdec */, X86::VAESDECZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10642   { 8086 /* vaesdeclast */, X86::VAESDECLASTrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10643   { 8086 /* vaesdeclast */, X86::VAESDECLASTYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10644   { 8086 /* vaesdeclast */, X86::VAESDECLASTZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10645   { 8086 /* vaesdeclast */, X86::VAESDECLASTZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10646   { 8086 /* vaesdeclast */, X86::VAESDECLASTZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10652   { 8098 /* vaesenc */, X86::VAESENCrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10653   { 8098 /* vaesenc */, X86::VAESENCYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10654   { 8098 /* vaesenc */, X86::VAESENCZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10655   { 8098 /* vaesenc */, X86::VAESENCZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10656   { 8098 /* vaesenc */, X86::VAESENCZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10662   { 8106 /* vaesenclast */, X86::VAESENCLASTrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10663   { 8106 /* vaesenclast */, X86::VAESENCLASTYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10664   { 8106 /* vaesenclast */, X86::VAESENCLASTZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10665   { 8106 /* vaesenclast */, X86::VAESENCLASTZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10666   { 8106 /* vaesenclast */, X86::VAESENCLASTZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10730   { 8159 /* vandnpd */, X86::VANDNPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10731   { 8159 /* vandnpd */, X86::VANDNPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10732   { 8159 /* vandnpd */, X86::VANDNPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10733   { 8159 /* vandnpd */, X86::VANDNPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10734   { 8159 /* vandnpd */, X86::VANDNPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10761   { 8167 /* vandnps */, X86::VANDNPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10762   { 8167 /* vandnps */, X86::VANDNPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10763   { 8167 /* vandnps */, X86::VANDNPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10764   { 8167 /* vandnps */, X86::VANDNPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10765   { 8167 /* vandnps */, X86::VANDNPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10792   { 8175 /* vandpd */, X86::VANDPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10793   { 8175 /* vandpd */, X86::VANDPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10794   { 8175 /* vandpd */, X86::VANDPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10795   { 8175 /* vandpd */, X86::VANDPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10796   { 8175 /* vandpd */, X86::VANDPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10823   { 8182 /* vandps */, X86::VANDPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
10824   { 8182 /* vandps */, X86::VANDPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
10825   { 8182 /* vandps */, X86::VANDPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10826   { 8182 /* vandps */, X86::VANDPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10827   { 8182 /* vandps */, X86::VANDPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10854   { 8189 /* vblendmpd */, X86::VBLENDMPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10855   { 8189 /* vblendmpd */, X86::VBLENDMPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10856   { 8189 /* vblendmpd */, X86::VBLENDMPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
10881   { 8199 /* vblendmps */, X86::VBLENDMPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
10882   { 8199 /* vblendmps */, X86::VBLENDMPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
10883   { 8199 /* vblendmps */, X86::VBLENDMPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
11197   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Z128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
11198   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Z256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
11199   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Zrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
11748   { 8876 /* vcvtsd2ss */, X86::VCVTSD2SSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
11749   { 8876 /* vcvtsd2ss */, X86::VCVTSD2SSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
11771   { 8921 /* vcvtsi2sd */, X86::VCVTSI2SDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32, MCK_FR32 }, },
11772   { 8921 /* vcvtsi2sd */, X86::VCVTSI2SDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X, MCK_FR32X }, },
11773   { 8921 /* vcvtsi2sd */, X86::VCVTSI642SDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32, MCK_FR32 }, },
11774   { 8921 /* vcvtsi2sd */, X86::VCVTSI642SDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X, MCK_FR32X }, },
11778   { 8931 /* vcvtsi2sdl */, X86::VCVTSI2SDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32, MCK_FR32 }, },
11779   { 8931 /* vcvtsi2sdl */, X86::VCVTSI2SDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X, MCK_FR32X }, },
11782   { 8942 /* vcvtsi2sdq */, X86::VCVTSI642SDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32, MCK_FR32 }, },
11783   { 8942 /* vcvtsi2sdq */, X86::VCVTSI642SDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X, MCK_FR32X }, },
11787   { 8953 /* vcvtsi2ss */, X86::VCVTSI2SSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32, MCK_FR32 }, },
11788   { 8953 /* vcvtsi2ss */, X86::VCVTSI2SSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X, MCK_FR32X }, },
11789   { 8953 /* vcvtsi2ss */, X86::VCVTSI642SSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32, MCK_FR32 }, },
11790   { 8953 /* vcvtsi2ss */, X86::VCVTSI642SSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X, MCK_FR32X }, },
11795   { 8963 /* vcvtsi2ssl */, X86::VCVTSI2SSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32, MCK_FR32 }, },
11796   { 8963 /* vcvtsi2ssl */, X86::VCVTSI2SSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X, MCK_FR32X }, },
11800   { 8974 /* vcvtsi2ssq */, X86::VCVTSI642SSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32, MCK_FR32 }, },
11801   { 8974 /* vcvtsi2ssq */, X86::VCVTSI642SSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X, MCK_FR32X }, },
11805   { 8985 /* vcvtss2sd */, X86::VCVTSS2SDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
11806   { 8985 /* vcvtss2sd */, X86::VCVTSS2SDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12315   { 9418 /* vcvtusi2sd */, X86::VCVTUSI2SDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X, MCK_FR32X }, },
12316   { 9418 /* vcvtusi2sd */, X86::VCVTUSI642SDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X, MCK_FR32X }, },
12319   { 9429 /* vcvtusi2sdl */, X86::VCVTUSI2SDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X, MCK_FR32X }, },
12321   { 9441 /* vcvtusi2sdq */, X86::VCVTUSI642SDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X, MCK_FR32X }, },
12324   { 9453 /* vcvtusi2ss */, X86::VCVTUSI2SSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X, MCK_FR32X }, },
12325   { 9453 /* vcvtusi2ss */, X86::VCVTUSI642SSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X, MCK_FR32X }, },
12329   { 9464 /* vcvtusi2ssl */, X86::VCVTUSI2SSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X, MCK_FR32X }, },
12332   { 9476 /* vcvtusi2ssq */, X86::VCVTUSI642SSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X, MCK_FR32X }, },
12353   { 9498 /* vdivpd */, X86::VDIVPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12354   { 9498 /* vdivpd */, X86::VDIVPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
12355   { 9498 /* vdivpd */, X86::VDIVPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12356   { 9498 /* vdivpd */, X86::VDIVPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12357   { 9498 /* vdivpd */, X86::VDIVPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
12387   { 9505 /* vdivps */, X86::VDIVPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12388   { 9505 /* vdivps */, X86::VDIVPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
12389   { 9505 /* vdivps */, X86::VDIVPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12390   { 9505 /* vdivps */, X86::VDIVPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
12391   { 9505 /* vdivps */, X86::VDIVPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
12421   { 9512 /* vdivsd */, X86::VDIVSDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12422   { 9512 /* vdivsd */, X86::VDIVSDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
12432   { 9519 /* vdivss */, X86::VDIVSSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
12433   { 9519 /* vdivss */, X86::VDIVSSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14438   { 11095 /* vgetexpsd */, X86::VGETEXPSDZr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14447   { 11105 /* vgetexpss */, X86::VGETEXPSSZr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14596   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14597   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14598   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14599   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14600   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14618   { 11203 /* vhaddpd */, X86::VHADDPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14619   { 11203 /* vhaddpd */, X86::VHADDPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14622   { 11211 /* vhaddps */, X86::VHADDPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14623   { 11211 /* vhaddps */, X86::VHADDPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14626   { 11219 /* vhsubpd */, X86::VHSUBPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14627   { 11219 /* vhsubpd */, X86::VHSUBPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14630   { 11227 /* vhsubps */, X86::VHSUBPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14631   { 11227 /* vhsubps */, X86::VHSUBPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14727   { 11423 /* vmaxpd */, X86::VMAXPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14728   { 11423 /* vmaxpd */, X86::VMAXPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14729   { 11423 /* vmaxpd */, X86::VMAXPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14730   { 11423 /* vmaxpd */, X86::VMAXPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14731   { 11423 /* vmaxpd */, X86::VMAXPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14761   { 11430 /* vmaxps */, X86::VMAXPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14762   { 11430 /* vmaxps */, X86::VMAXPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14763   { 11430 /* vmaxps */, X86::VMAXPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14764   { 11430 /* vmaxps */, X86::VMAXPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14765   { 11430 /* vmaxps */, X86::VMAXPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14795   { 11437 /* vmaxsd */, X86::VMAXSDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14796   { 11437 /* vmaxsd */, X86::VMAXSDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14806   { 11444 /* vmaxss */, X86::VMAXSSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14807   { 11444 /* vmaxss */, X86::VMAXSSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14820   { 11473 /* vminpd */, X86::VMINPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14821   { 11473 /* vminpd */, X86::VMINPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14822   { 11473 /* vminpd */, X86::VMINPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14823   { 11473 /* vminpd */, X86::VMINPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14824   { 11473 /* vminpd */, X86::VMINPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14854   { 11480 /* vminps */, X86::VMINPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14855   { 11480 /* vminps */, X86::VMINPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
14856   { 11480 /* vminps */, X86::VMINPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14857   { 11480 /* vminps */, X86::VMINPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
14858   { 11480 /* vminps */, X86::VMINPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
14888   { 11487 /* vminsd */, X86::VMINSDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14889   { 11487 /* vminsd */, X86::VMINSDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
14899   { 11494 /* vminss */, X86::VMINSSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
14900   { 11494 /* vminss */, X86::VMINSSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15244   { 11742 /* vmovhlps */, X86::VMOVHLPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15245   { 11742 /* vmovhlps */, X86::VMOVHLPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15254   { 11767 /* vmovlhps */, X86::VMOVLHPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15255   { 11767 /* vmovlhps */, X86::VMOVLHPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15304   { 11863 /* vmovsd */, X86::VMOVSDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15305   { 11863 /* vmovsd */, X86::VMOVSDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15311   { 11870 /* vmovsd.s */, X86::VMOVSDrr_REV, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15312   { 11870 /* vmovsd.s */, X86::VMOVSDZrr_REV, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15363   { 11899 /* vmovss */, X86::VMOVSSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15364   { 11899 /* vmovss */, X86::VMOVSSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15370   { 11906 /* vmovss.s */, X86::VMOVSSrr_REV, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15371   { 11906 /* vmovss.s */, X86::VMOVSSZrr_REV, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15471   { 12021 /* vmulpd */, X86::VMULPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15472   { 12021 /* vmulpd */, X86::VMULPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15473   { 12021 /* vmulpd */, X86::VMULPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15474   { 12021 /* vmulpd */, X86::VMULPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15475   { 12021 /* vmulpd */, X86::VMULPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15505   { 12028 /* vmulps */, X86::VMULPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15506   { 12028 /* vmulps */, X86::VMULPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15507   { 12028 /* vmulps */, X86::VMULPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15508   { 12028 /* vmulps */, X86::VMULPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15509   { 12028 /* vmulps */, X86::VMULPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15539   { 12035 /* vmulsd */, X86::VMULSDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15540   { 12035 /* vmulsd */, X86::VMULSDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15550   { 12042 /* vmulss */, X86::VMULSSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15551   { 12042 /* vmulss */, X86::VMULSSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15567   { 12088 /* vorpd */, X86::VORPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15568   { 12088 /* vorpd */, X86::VORPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15569   { 12088 /* vorpd */, X86::VORPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15570   { 12088 /* vorpd */, X86::VORPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15571   { 12088 /* vorpd */, X86::VORPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15598   { 12094 /* vorps */, X86::VORPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15599   { 12094 /* vorps */, X86::VORPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15600   { 12094 /* vorps */, X86::VORPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15601   { 12094 /* vorps */, X86::VORPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15602   { 12094 /* vorps */, X86::VORPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15755   { 12177 /* vpackssdw */, X86::VPACKSSDWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15756   { 12177 /* vpackssdw */, X86::VPACKSSDWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15757   { 12177 /* vpackssdw */, X86::VPACKSSDWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15758   { 12177 /* vpackssdw */, X86::VPACKSSDWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15759   { 12177 /* vpackssdw */, X86::VPACKSSDWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15786   { 12187 /* vpacksswb */, X86::VPACKSSWBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15787   { 12187 /* vpacksswb */, X86::VPACKSSWBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15788   { 12187 /* vpacksswb */, X86::VPACKSSWBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15789   { 12187 /* vpacksswb */, X86::VPACKSSWBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15790   { 12187 /* vpacksswb */, X86::VPACKSSWBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15808   { 12197 /* vpackusdw */, X86::VPACKUSDWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15809   { 12197 /* vpackusdw */, X86::VPACKUSDWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15810   { 12197 /* vpackusdw */, X86::VPACKUSDWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15811   { 12197 /* vpackusdw */, X86::VPACKUSDWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15812   { 12197 /* vpackusdw */, X86::VPACKUSDWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15839   { 12207 /* vpackuswb */, X86::VPACKUSWBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15840   { 12207 /* vpackuswb */, X86::VPACKUSWBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15841   { 12207 /* vpackuswb */, X86::VPACKUSWBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15842   { 12207 /* vpackuswb */, X86::VPACKUSWBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15843   { 12207 /* vpackuswb */, X86::VPACKUSWBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15861   { 12217 /* vpaddb */, X86::VPADDBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15862   { 12217 /* vpaddb */, X86::VPADDBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15863   { 12217 /* vpaddb */, X86::VPADDBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15864   { 12217 /* vpaddb */, X86::VPADDBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15865   { 12217 /* vpaddb */, X86::VPADDBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15883   { 12224 /* vpaddd */, X86::VPADDDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15884   { 12224 /* vpaddd */, X86::VPADDDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15885   { 12224 /* vpaddd */, X86::VPADDDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15886   { 12224 /* vpaddd */, X86::VPADDDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15887   { 12224 /* vpaddd */, X86::VPADDDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15914   { 12231 /* vpaddq */, X86::VPADDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15915   { 12231 /* vpaddq */, X86::VPADDQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15916   { 12231 /* vpaddq */, X86::VPADDQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15917   { 12231 /* vpaddq */, X86::VPADDQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15918   { 12231 /* vpaddq */, X86::VPADDQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15945   { 12238 /* vpaddsb */, X86::VPADDSBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15946   { 12238 /* vpaddsb */, X86::VPADDSBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15947   { 12238 /* vpaddsb */, X86::VPADDSBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15948   { 12238 /* vpaddsb */, X86::VPADDSBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15949   { 12238 /* vpaddsb */, X86::VPADDSBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15967   { 12246 /* vpaddsw */, X86::VPADDSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15968   { 12246 /* vpaddsw */, X86::VPADDSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15969   { 12246 /* vpaddsw */, X86::VPADDSWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15970   { 12246 /* vpaddsw */, X86::VPADDSWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15971   { 12246 /* vpaddsw */, X86::VPADDSWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
15989   { 12254 /* vpaddusb */, X86::VPADDUSBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
15990   { 12254 /* vpaddusb */, X86::VPADDUSBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
15991   { 12254 /* vpaddusb */, X86::VPADDUSBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
15992   { 12254 /* vpaddusb */, X86::VPADDUSBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
15993   { 12254 /* vpaddusb */, X86::VPADDUSBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16011   { 12263 /* vpaddusw */, X86::VPADDUSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16012   { 12263 /* vpaddusw */, X86::VPADDUSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16013   { 12263 /* vpaddusw */, X86::VPADDUSWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16014   { 12263 /* vpaddusw */, X86::VPADDUSWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16015   { 12263 /* vpaddusw */, X86::VPADDUSWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16033   { 12272 /* vpaddw */, X86::VPADDWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16034   { 12272 /* vpaddw */, X86::VPADDWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16035   { 12272 /* vpaddw */, X86::VPADDWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16036   { 12272 /* vpaddw */, X86::VPADDWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16037   { 12272 /* vpaddw */, X86::VPADDWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16077   { 12288 /* vpand */, X86::VPANDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16078   { 12288 /* vpand */, X86::VPANDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16081   { 12294 /* vpandd */, X86::VPANDDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16082   { 12294 /* vpandd */, X86::VPANDDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16083   { 12294 /* vpandd */, X86::VPANDDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16108   { 12301 /* vpandn */, X86::VPANDNrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16109   { 12301 /* vpandn */, X86::VPANDNYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16112   { 12308 /* vpandnd */, X86::VPANDNDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16113   { 12308 /* vpandnd */, X86::VPANDNDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16114   { 12308 /* vpandnd */, X86::VPANDNDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16139   { 12316 /* vpandnq */, X86::VPANDNQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16140   { 12316 /* vpandnq */, X86::VPANDNQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16141   { 12316 /* vpandnq */, X86::VPANDNQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16166   { 12324 /* vpandq */, X86::VPANDQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16167   { 12324 /* vpandq */, X86::VPANDQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16168   { 12324 /* vpandq */, X86::VPANDQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16193   { 12331 /* vpavgb */, X86::VPAVGBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16194   { 12331 /* vpavgb */, X86::VPAVGBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16195   { 12331 /* vpavgb */, X86::VPAVGBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16196   { 12331 /* vpavgb */, X86::VPAVGBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16197   { 12331 /* vpavgb */, X86::VPAVGBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16215   { 12338 /* vpavgw */, X86::VPAVGWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16216   { 12338 /* vpavgw */, X86::VPAVGWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16217   { 12338 /* vpavgw */, X86::VPAVGWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16218   { 12338 /* vpavgw */, X86::VPAVGWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16219   { 12338 /* vpavgw */, X86::VPAVGWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16241   { 12354 /* vpblendmb */, X86::VPBLENDMBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16242   { 12354 /* vpblendmb */, X86::VPBLENDMBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16243   { 12354 /* vpblendmb */, X86::VPBLENDMBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16259   { 12364 /* vpblendmd */, X86::VPBLENDMDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16260   { 12364 /* vpblendmd */, X86::VPBLENDMDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16261   { 12364 /* vpblendmd */, X86::VPBLENDMDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16286   { 12374 /* vpblendmq */, X86::VPBLENDMQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16287   { 12374 /* vpblendmq */, X86::VPBLENDMQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16288   { 12374 /* vpblendmq */, X86::VPBLENDMQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16313   { 12384 /* vpblendmw */, X86::VPBLENDMWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
16314   { 12384 /* vpblendmw */, X86::VPBLENDMWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
16315   { 12384 /* vpblendmw */, X86::VPBLENDMWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
16555   { 12585 /* vpcmpeqb */, X86::VPCMPEQBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16556   { 12585 /* vpcmpeqb */, X86::VPCMPEQBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16557   { 12585 /* vpcmpeqb */, X86::VPCMPEQBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
16558   { 12585 /* vpcmpeqb */, X86::VPCMPEQBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
16559   { 12585 /* vpcmpeqb */, X86::VPCMPEQBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
16571   { 12594 /* vpcmpeqd */, X86::VPCMPEQDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16572   { 12594 /* vpcmpeqd */, X86::VPCMPEQDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16573   { 12594 /* vpcmpeqd */, X86::VPCMPEQDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
16574   { 12594 /* vpcmpeqd */, X86::VPCMPEQDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
16575   { 12594 /* vpcmpeqd */, X86::VPCMPEQDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
16593   { 12603 /* vpcmpeqq */, X86::VPCMPEQQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16594   { 12603 /* vpcmpeqq */, X86::VPCMPEQQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16595   { 12603 /* vpcmpeqq */, X86::VPCMPEQQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
16596   { 12603 /* vpcmpeqq */, X86::VPCMPEQQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
16597   { 12603 /* vpcmpeqq */, X86::VPCMPEQQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
16615   { 12612 /* vpcmpeqw */, X86::VPCMPEQWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16616   { 12612 /* vpcmpeqw */, X86::VPCMPEQWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16617   { 12612 /* vpcmpeqw */, X86::VPCMPEQWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
16618   { 12612 /* vpcmpeqw */, X86::VPCMPEQWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
16619   { 12612 /* vpcmpeqw */, X86::VPCMPEQWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
16635   { 12643 /* vpcmpgtb */, X86::VPCMPGTBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16636   { 12643 /* vpcmpgtb */, X86::VPCMPGTBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16637   { 12643 /* vpcmpgtb */, X86::VPCMPGTBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
16638   { 12643 /* vpcmpgtb */, X86::VPCMPGTBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
16639   { 12643 /* vpcmpgtb */, X86::VPCMPGTBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
16651   { 12652 /* vpcmpgtd */, X86::VPCMPGTDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16652   { 12652 /* vpcmpgtd */, X86::VPCMPGTDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16653   { 12652 /* vpcmpgtd */, X86::VPCMPGTDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
16654   { 12652 /* vpcmpgtd */, X86::VPCMPGTDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
16655   { 12652 /* vpcmpgtd */, X86::VPCMPGTDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
16673   { 12661 /* vpcmpgtq */, X86::VPCMPGTQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16674   { 12661 /* vpcmpgtq */, X86::VPCMPGTQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16675   { 12661 /* vpcmpgtq */, X86::VPCMPGTQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
16676   { 12661 /* vpcmpgtq */, X86::VPCMPGTQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
16677   { 12661 /* vpcmpgtq */, X86::VPCMPGTQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
16695   { 12670 /* vpcmpgtw */, X86::VPCMPGTWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
16696   { 12670 /* vpcmpgtw */, X86::VPCMPGTWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
16697   { 12670 /* vpcmpgtw */, X86::VPCMPGTWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
16698   { 12670 /* vpcmpgtw */, X86::VPCMPGTWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
16699   { 12670 /* vpcmpgtw */, X86::VPCMPGTWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
17047   { 12939 /* vpermb */, X86::VPERMBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17048   { 12939 /* vpermb */, X86::VPERMBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17049   { 12939 /* vpermb */, X86::VPERMBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17065   { 12946 /* vpermd */, X86::VPERMDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17066   { 12946 /* vpermd */, X86::VPERMDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17067   { 12946 /* vpermd */, X86::VPERMDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17241   { 13031 /* vpermilpd */, X86::VPERMILPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17242   { 13031 /* vpermilpd */, X86::VPERMILPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17243   { 13031 /* vpermilpd */, X86::VPERMILPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17244   { 13031 /* vpermilpd */, X86::VPERMILPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17245   { 13031 /* vpermilpd */, X86::VPERMILPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17303   { 13041 /* vpermilps */, X86::VPERMILPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17304   { 13041 /* vpermilps */, X86::VPERMILPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17305   { 13041 /* vpermilps */, X86::VPERMILPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17306   { 13041 /* vpermilps */, X86::VPERMILPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17307   { 13041 /* vpermilps */, X86::VPERMILPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17365   { 13051 /* vpermpd */, X86::VPERMPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17366   { 13051 /* vpermpd */, X86::VPERMPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17403   { 13059 /* vpermps */, X86::VPERMPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17404   { 13059 /* vpermps */, X86::VPERMPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17405   { 13059 /* vpermps */, X86::VPERMPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17423   { 13067 /* vpermq */, X86::VPERMQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17424   { 13067 /* vpermq */, X86::VPERMQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17605   { 13130 /* vpermw */, X86::VPERMWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17606   { 13130 /* vpermw */, X86::VPERMWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17607   { 13130 /* vpermw */, X86::VPERMWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17737   { 13280 /* vphaddd */, X86::VPHADDDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17738   { 13280 /* vphaddd */, X86::VPHADDDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17743   { 13297 /* vphaddsw */, X86::VPHADDSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17744   { 13297 /* vphaddsw */, X86::VPHADDSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17759   { 13366 /* vphaddw */, X86::VPHADDWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17760   { 13366 /* vphaddw */, X86::VPHADDWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17771   { 13413 /* vphsubd */, X86::VPHSUBDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17772   { 13413 /* vphsubd */, X86::VPHSUBDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17777   { 13430 /* vphsubsw */, X86::VPHSUBSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17778   { 13430 /* vphsubsw */, X86::VPHSUBSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17781   { 13439 /* vphsubw */, X86::VPHSUBWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17782   { 13439 /* vphsubw */, X86::VPHSUBWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17935   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17936   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17937   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17938   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17939   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17957   { 13661 /* vpmaddwd */, X86::VPMADDWDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17958   { 13661 /* vpmaddwd */, X86::VPMADDWDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17959   { 13661 /* vpmaddwd */, X86::VPMADDWDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17960   { 13661 /* vpmaddwd */, X86::VPMADDWDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17961   { 13661 /* vpmaddwd */, X86::VPMADDWDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
17987   { 13692 /* vpmaxsb */, X86::VPMAXSBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
17988   { 13692 /* vpmaxsb */, X86::VPMAXSBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
17989   { 13692 /* vpmaxsb */, X86::VPMAXSBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
17990   { 13692 /* vpmaxsb */, X86::VPMAXSBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
17991   { 13692 /* vpmaxsb */, X86::VPMAXSBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18009   { 13700 /* vpmaxsd */, X86::VPMAXSDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18010   { 13700 /* vpmaxsd */, X86::VPMAXSDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18011   { 13700 /* vpmaxsd */, X86::VPMAXSDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18012   { 13700 /* vpmaxsd */, X86::VPMAXSDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18013   { 13700 /* vpmaxsd */, X86::VPMAXSDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18040   { 13708 /* vpmaxsq */, X86::VPMAXSQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18041   { 13708 /* vpmaxsq */, X86::VPMAXSQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18042   { 13708 /* vpmaxsq */, X86::VPMAXSQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18067   { 13716 /* vpmaxsw */, X86::VPMAXSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18068   { 13716 /* vpmaxsw */, X86::VPMAXSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18069   { 13716 /* vpmaxsw */, X86::VPMAXSWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18070   { 13716 /* vpmaxsw */, X86::VPMAXSWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18071   { 13716 /* vpmaxsw */, X86::VPMAXSWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18089   { 13724 /* vpmaxub */, X86::VPMAXUBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18090   { 13724 /* vpmaxub */, X86::VPMAXUBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18091   { 13724 /* vpmaxub */, X86::VPMAXUBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18092   { 13724 /* vpmaxub */, X86::VPMAXUBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18093   { 13724 /* vpmaxub */, X86::VPMAXUBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18111   { 13732 /* vpmaxud */, X86::VPMAXUDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18112   { 13732 /* vpmaxud */, X86::VPMAXUDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18113   { 13732 /* vpmaxud */, X86::VPMAXUDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18114   { 13732 /* vpmaxud */, X86::VPMAXUDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18115   { 13732 /* vpmaxud */, X86::VPMAXUDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18142   { 13740 /* vpmaxuq */, X86::VPMAXUQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18143   { 13740 /* vpmaxuq */, X86::VPMAXUQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18144   { 13740 /* vpmaxuq */, X86::VPMAXUQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18169   { 13748 /* vpmaxuw */, X86::VPMAXUWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18170   { 13748 /* vpmaxuw */, X86::VPMAXUWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18171   { 13748 /* vpmaxuw */, X86::VPMAXUWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18172   { 13748 /* vpmaxuw */, X86::VPMAXUWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18173   { 13748 /* vpmaxuw */, X86::VPMAXUWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18191   { 13756 /* vpminsb */, X86::VPMINSBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18192   { 13756 /* vpminsb */, X86::VPMINSBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18193   { 13756 /* vpminsb */, X86::VPMINSBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18194   { 13756 /* vpminsb */, X86::VPMINSBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18195   { 13756 /* vpminsb */, X86::VPMINSBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18213   { 13764 /* vpminsd */, X86::VPMINSDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18214   { 13764 /* vpminsd */, X86::VPMINSDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18215   { 13764 /* vpminsd */, X86::VPMINSDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18216   { 13764 /* vpminsd */, X86::VPMINSDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18217   { 13764 /* vpminsd */, X86::VPMINSDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18244   { 13772 /* vpminsq */, X86::VPMINSQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18245   { 13772 /* vpminsq */, X86::VPMINSQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18246   { 13772 /* vpminsq */, X86::VPMINSQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18271   { 13780 /* vpminsw */, X86::VPMINSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18272   { 13780 /* vpminsw */, X86::VPMINSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18273   { 13780 /* vpminsw */, X86::VPMINSWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18274   { 13780 /* vpminsw */, X86::VPMINSWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18275   { 13780 /* vpminsw */, X86::VPMINSWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18293   { 13788 /* vpminub */, X86::VPMINUBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18294   { 13788 /* vpminub */, X86::VPMINUBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18295   { 13788 /* vpminub */, X86::VPMINUBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18296   { 13788 /* vpminub */, X86::VPMINUBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18297   { 13788 /* vpminub */, X86::VPMINUBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18315   { 13796 /* vpminud */, X86::VPMINUDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18316   { 13796 /* vpminud */, X86::VPMINUDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18317   { 13796 /* vpminud */, X86::VPMINUDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18318   { 13796 /* vpminud */, X86::VPMINUDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18319   { 13796 /* vpminud */, X86::VPMINUDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18346   { 13804 /* vpminuq */, X86::VPMINUQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18347   { 13804 /* vpminuq */, X86::VPMINUQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18348   { 13804 /* vpminuq */, X86::VPMINUQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18373   { 13812 /* vpminuw */, X86::VPMINUWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18374   { 13812 /* vpminuw */, X86::VPMINUWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18375   { 13812 /* vpminuw */, X86::VPMINUWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18376   { 13812 /* vpminuw */, X86::VPMINUWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18377   { 13812 /* vpminuw */, X86::VPMINUWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18955   { 14184 /* vpmuldq */, X86::VPMULDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18956   { 14184 /* vpmuldq */, X86::VPMULDQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18957   { 14184 /* vpmuldq */, X86::VPMULDQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18958   { 14184 /* vpmuldq */, X86::VPMULDQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18959   { 14184 /* vpmuldq */, X86::VPMULDQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
18986   { 14192 /* vpmulhrsw */, X86::VPMULHRSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
18987   { 14192 /* vpmulhrsw */, X86::VPMULHRSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
18988   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
18989   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
18990   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19008   { 14202 /* vpmulhuw */, X86::VPMULHUWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19009   { 14202 /* vpmulhuw */, X86::VPMULHUWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
19010   { 14202 /* vpmulhuw */, X86::VPMULHUWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19011   { 14202 /* vpmulhuw */, X86::VPMULHUWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19012   { 14202 /* vpmulhuw */, X86::VPMULHUWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19030   { 14211 /* vpmulhw */, X86::VPMULHWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19031   { 14211 /* vpmulhw */, X86::VPMULHWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
19032   { 14211 /* vpmulhw */, X86::VPMULHWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19033   { 14211 /* vpmulhw */, X86::VPMULHWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19034   { 14211 /* vpmulhw */, X86::VPMULHWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19052   { 14219 /* vpmulld */, X86::VPMULLDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19053   { 14219 /* vpmulld */, X86::VPMULLDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
19054   { 14219 /* vpmulld */, X86::VPMULLDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19055   { 14219 /* vpmulld */, X86::VPMULLDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19056   { 14219 /* vpmulld */, X86::VPMULLDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19083   { 14227 /* vpmullq */, X86::VPMULLQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19084   { 14227 /* vpmullq */, X86::VPMULLQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19085   { 14227 /* vpmullq */, X86::VPMULLQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19110   { 14235 /* vpmullw */, X86::VPMULLWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19111   { 14235 /* vpmullw */, X86::VPMULLWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
19112   { 14235 /* vpmullw */, X86::VPMULLWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19113   { 14235 /* vpmullw */, X86::VPMULLWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19114   { 14235 /* vpmullw */, X86::VPMULLWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19132   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19133   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19134   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19159   { 14258 /* vpmuludq */, X86::VPMULUDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19160   { 14258 /* vpmuludq */, X86::VPMULUDQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
19161   { 14258 /* vpmuludq */, X86::VPMULUDQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19162   { 14258 /* vpmuludq */, X86::VPMULUDQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19163   { 14258 /* vpmuludq */, X86::VPMULUDQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19280   { 14303 /* vpor */, X86::VPORrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19281   { 14303 /* vpor */, X86::VPORYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
19284   { 14308 /* vpord */, X86::VPORDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19285   { 14308 /* vpord */, X86::VPORDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19286   { 14308 /* vpord */, X86::VPORDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19311   { 14314 /* vporq */, X86::VPORQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19312   { 14314 /* vporq */, X86::VPORQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19313   { 14314 /* vporq */, X86::VPORQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19395   { 14341 /* vprolvd */, X86::VPROLVDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19396   { 14341 /* vprolvd */, X86::VPROLVDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19397   { 14341 /* vprolvd */, X86::VPROLVDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19422   { 14349 /* vprolvq */, X86::VPROLVQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19423   { 14349 /* vprolvq */, X86::VPROLVQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19424   { 14349 /* vprolvq */, X86::VPROLVQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19503   { 14371 /* vprorvd */, X86::VPRORVDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19504   { 14371 /* vprorvd */, X86::VPRORVDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19505   { 14371 /* vprorvd */, X86::VPRORVDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19530   { 14379 /* vprorvq */, X86::VPRORVQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19531   { 14379 /* vprorvq */, X86::VPRORVQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19532   { 14379 /* vprorvq */, X86::VPRORVQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19557   { 14387 /* vprotb */, X86::VPROTBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19562   { 14394 /* vprotd */, X86::VPROTDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19567   { 14401 /* vprotq */, X86::VPROTQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19572   { 14408 /* vprotw */, X86::VPROTWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19577   { 14415 /* vpsadbw */, X86::VPSADBWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19578   { 14415 /* vpsadbw */, X86::VPSADBWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
19579   { 14415 /* vpsadbw */, X86::VPSADBWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19580   { 14415 /* vpsadbw */, X86::VPSADBWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19581   { 14415 /* vpsadbw */, X86::VPSADBWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19599   { 14471 /* vpshab */, X86::VPSHABrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19602   { 14478 /* vpshad */, X86::VPSHADrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19605   { 14485 /* vpshaq */, X86::VPSHAQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19608   { 14492 /* vpshaw */, X86::VPSHAWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19611   { 14499 /* vpshlb */, X86::VPSHLBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19614   { 14506 /* vpshld */, X86::VPSHLDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19761   { 14564 /* vpshlq */, X86::VPSHLQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19764   { 14571 /* vpshlw */, X86::VPSHLWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19911   { 14629 /* vpshufb */, X86::VPSHUFBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
19912   { 14629 /* vpshufb */, X86::VPSHUFBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
19913   { 14629 /* vpshufb */, X86::VPSHUFBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
19914   { 14629 /* vpshufb */, X86::VPSHUFBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
19915   { 14629 /* vpshufb */, X86::VPSHUFBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
19933   { 14637 /* vpshufbitqmb */, X86::VPSHUFBITQMBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
19934   { 14637 /* vpshufbitqmb */, X86::VPSHUFBITQMBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
19935   { 14637 /* vpshufbitqmb */, X86::VPSHUFBITQMBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
20020   { 14676 /* vpsignb */, X86::VPSIGNBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20021   { 14676 /* vpsignb */, X86::VPSIGNBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20024   { 14684 /* vpsignd */, X86::VPSIGNDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20025   { 14684 /* vpsignd */, X86::VPSIGNDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20028   { 14692 /* vpsignw */, X86::VPSIGNWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20029   { 14692 /* vpsignw */, X86::VPSIGNWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20032   { 14700 /* vpslld */, X86::VPSLLDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20033   { 14700 /* vpslld */, X86::VPSLLDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256, MCK_VR256 }, },
20034   { 14700 /* vpslld */, X86::VPSLLDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20035   { 14700 /* vpslld */, X86::VPSLLDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X, MCK_VR256X }, },
20036   { 14700 /* vpslld */, X86::VPSLLDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512, MCK_VR512 }, },
20091   { 14715 /* vpsllq */, X86::VPSLLQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20092   { 14715 /* vpsllq */, X86::VPSLLQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256, MCK_VR256 }, },
20093   { 14715 /* vpsllq */, X86::VPSLLQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20094   { 14715 /* vpsllq */, X86::VPSLLQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X, MCK_VR256X }, },
20095   { 14715 /* vpsllq */, X86::VPSLLQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512, MCK_VR512 }, },
20142   { 14722 /* vpsllvd */, X86::VPSLLVDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20143   { 14722 /* vpsllvd */, X86::VPSLLVDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20144   { 14722 /* vpsllvd */, X86::VPSLLVDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20145   { 14722 /* vpsllvd */, X86::VPSLLVDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20146   { 14722 /* vpsllvd */, X86::VPSLLVDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20173   { 14730 /* vpsllvq */, X86::VPSLLVQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20174   { 14730 /* vpsllvq */, X86::VPSLLVQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20175   { 14730 /* vpsllvq */, X86::VPSLLVQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20176   { 14730 /* vpsllvq */, X86::VPSLLVQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20177   { 14730 /* vpsllvq */, X86::VPSLLVQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20204   { 14738 /* vpsllvw */, X86::VPSLLVWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20205   { 14738 /* vpsllvw */, X86::VPSLLVWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20206   { 14738 /* vpsllvw */, X86::VPSLLVWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20222   { 14746 /* vpsllw */, X86::VPSLLWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20223   { 14746 /* vpsllw */, X86::VPSLLWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256, MCK_VR256 }, },
20224   { 14746 /* vpsllw */, X86::VPSLLWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20225   { 14746 /* vpsllw */, X86::VPSLLWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X, MCK_VR256X }, },
20226   { 14746 /* vpsllw */, X86::VPSLLWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512, MCK_VR512 }, },
20264   { 14753 /* vpsrad */, X86::VPSRADrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20265   { 14753 /* vpsrad */, X86::VPSRADYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256, MCK_VR256 }, },
20266   { 14753 /* vpsrad */, X86::VPSRADZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20267   { 14753 /* vpsrad */, X86::VPSRADZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X, MCK_VR256X }, },
20268   { 14753 /* vpsrad */, X86::VPSRADZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512, MCK_VR512 }, },
20315   { 14760 /* vpsraq */, X86::VPSRAQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20316   { 14760 /* vpsraq */, X86::VPSRAQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X, MCK_VR256X }, },
20317   { 14760 /* vpsraq */, X86::VPSRAQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512, MCK_VR512 }, },
20360   { 14767 /* vpsravd */, X86::VPSRAVDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20361   { 14767 /* vpsravd */, X86::VPSRAVDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20362   { 14767 /* vpsravd */, X86::VPSRAVDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20363   { 14767 /* vpsravd */, X86::VPSRAVDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20364   { 14767 /* vpsravd */, X86::VPSRAVDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20391   { 14775 /* vpsravq */, X86::VPSRAVQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20392   { 14775 /* vpsravq */, X86::VPSRAVQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20393   { 14775 /* vpsravq */, X86::VPSRAVQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20418   { 14783 /* vpsravw */, X86::VPSRAVWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20419   { 14783 /* vpsravw */, X86::VPSRAVWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20420   { 14783 /* vpsravw */, X86::VPSRAVWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20436   { 14791 /* vpsraw */, X86::VPSRAWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20437   { 14791 /* vpsraw */, X86::VPSRAWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256, MCK_VR256 }, },
20438   { 14791 /* vpsraw */, X86::VPSRAWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20439   { 14791 /* vpsraw */, X86::VPSRAWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X, MCK_VR256X }, },
20440   { 14791 /* vpsraw */, X86::VPSRAWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512, MCK_VR512 }, },
20478   { 14798 /* vpsrld */, X86::VPSRLDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20479   { 14798 /* vpsrld */, X86::VPSRLDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256, MCK_VR256 }, },
20480   { 14798 /* vpsrld */, X86::VPSRLDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20481   { 14798 /* vpsrld */, X86::VPSRLDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X, MCK_VR256X }, },
20482   { 14798 /* vpsrld */, X86::VPSRLDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512, MCK_VR512 }, },
20537   { 14813 /* vpsrlq */, X86::VPSRLQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20538   { 14813 /* vpsrlq */, X86::VPSRLQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256, MCK_VR256 }, },
20539   { 14813 /* vpsrlq */, X86::VPSRLQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20540   { 14813 /* vpsrlq */, X86::VPSRLQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X, MCK_VR256X }, },
20541   { 14813 /* vpsrlq */, X86::VPSRLQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512, MCK_VR512 }, },
20588   { 14820 /* vpsrlvd */, X86::VPSRLVDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20589   { 14820 /* vpsrlvd */, X86::VPSRLVDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20590   { 14820 /* vpsrlvd */, X86::VPSRLVDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20591   { 14820 /* vpsrlvd */, X86::VPSRLVDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20592   { 14820 /* vpsrlvd */, X86::VPSRLVDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20619   { 14828 /* vpsrlvq */, X86::VPSRLVQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20620   { 14828 /* vpsrlvq */, X86::VPSRLVQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20621   { 14828 /* vpsrlvq */, X86::VPSRLVQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20622   { 14828 /* vpsrlvq */, X86::VPSRLVQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20623   { 14828 /* vpsrlvq */, X86::VPSRLVQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20650   { 14836 /* vpsrlvw */, X86::VPSRLVWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20651   { 14836 /* vpsrlvw */, X86::VPSRLVWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20652   { 14836 /* vpsrlvw */, X86::VPSRLVWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20668   { 14844 /* vpsrlw */, X86::VPSRLWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20669   { 14844 /* vpsrlw */, X86::VPSRLWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256, MCK_VR256 }, },
20670   { 14844 /* vpsrlw */, X86::VPSRLWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20671   { 14844 /* vpsrlw */, X86::VPSRLWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X, MCK_VR256X }, },
20672   { 14844 /* vpsrlw */, X86::VPSRLWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512, MCK_VR512 }, },
20710   { 14851 /* vpsubb */, X86::VPSUBBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20711   { 14851 /* vpsubb */, X86::VPSUBBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20712   { 14851 /* vpsubb */, X86::VPSUBBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20713   { 14851 /* vpsubb */, X86::VPSUBBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20714   { 14851 /* vpsubb */, X86::VPSUBBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20732   { 14858 /* vpsubd */, X86::VPSUBDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20733   { 14858 /* vpsubd */, X86::VPSUBDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20734   { 14858 /* vpsubd */, X86::VPSUBDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20735   { 14858 /* vpsubd */, X86::VPSUBDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20736   { 14858 /* vpsubd */, X86::VPSUBDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20763   { 14865 /* vpsubq */, X86::VPSUBQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20764   { 14865 /* vpsubq */, X86::VPSUBQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20765   { 14865 /* vpsubq */, X86::VPSUBQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20766   { 14865 /* vpsubq */, X86::VPSUBQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20767   { 14865 /* vpsubq */, X86::VPSUBQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20794   { 14872 /* vpsubsb */, X86::VPSUBSBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20795   { 14872 /* vpsubsb */, X86::VPSUBSBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20796   { 14872 /* vpsubsb */, X86::VPSUBSBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20797   { 14872 /* vpsubsb */, X86::VPSUBSBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20798   { 14872 /* vpsubsb */, X86::VPSUBSBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20816   { 14880 /* vpsubsw */, X86::VPSUBSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20817   { 14880 /* vpsubsw */, X86::VPSUBSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20818   { 14880 /* vpsubsw */, X86::VPSUBSWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20819   { 14880 /* vpsubsw */, X86::VPSUBSWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20820   { 14880 /* vpsubsw */, X86::VPSUBSWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20838   { 14888 /* vpsubusb */, X86::VPSUBUSBrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20839   { 14888 /* vpsubusb */, X86::VPSUBUSBYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20840   { 14888 /* vpsubusb */, X86::VPSUBUSBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20841   { 14888 /* vpsubusb */, X86::VPSUBUSBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20842   { 14888 /* vpsubusb */, X86::VPSUBUSBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20860   { 14897 /* vpsubusw */, X86::VPSUBUSWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20861   { 14897 /* vpsubusw */, X86::VPSUBUSWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20862   { 14897 /* vpsubusw */, X86::VPSUBUSWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20863   { 14897 /* vpsubusw */, X86::VPSUBUSWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20864   { 14897 /* vpsubusw */, X86::VPSUBUSWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20882   { 14906 /* vpsubw */, X86::VPSUBWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
20883   { 14906 /* vpsubw */, X86::VPSUBWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
20884   { 14906 /* vpsubw */, X86::VPSUBWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
20885   { 14906 /* vpsubw */, X86::VPSUBWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
20886   { 14906 /* vpsubw */, X86::VPSUBWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
20962   { 14942 /* vptestmb */, X86::VPTESTMBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
20963   { 14942 /* vptestmb */, X86::VPTESTMBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
20964   { 14942 /* vptestmb */, X86::VPTESTMBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
20974   { 14951 /* vptestmd */, X86::VPTESTMDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
20975   { 14951 /* vptestmd */, X86::VPTESTMDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
20976   { 14951 /* vptestmd */, X86::VPTESTMDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
20992   { 14960 /* vptestmq */, X86::VPTESTMQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
20993   { 14960 /* vptestmq */, X86::VPTESTMQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
20994   { 14960 /* vptestmq */, X86::VPTESTMQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
21010   { 14969 /* vptestmw */, X86::VPTESTMWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
21011   { 14969 /* vptestmw */, X86::VPTESTMWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
21012   { 14969 /* vptestmw */, X86::VPTESTMWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
21022   { 14978 /* vptestnmb */, X86::VPTESTNMBZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
21023   { 14978 /* vptestnmb */, X86::VPTESTNMBZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
21024   { 14978 /* vptestnmb */, X86::VPTESTNMBZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
21034   { 14988 /* vptestnmd */, X86::VPTESTNMDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
21035   { 14988 /* vptestnmd */, X86::VPTESTNMDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
21036   { 14988 /* vptestnmd */, X86::VPTESTNMDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
21052   { 14998 /* vptestnmq */, X86::VPTESTNMQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
21053   { 14998 /* vptestnmq */, X86::VPTESTNMQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
21054   { 14998 /* vptestnmq */, X86::VPTESTNMQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
21070   { 15008 /* vptestnmw */, X86::VPTESTNMWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_VK1 }, },
21071   { 15008 /* vptestnmw */, X86::VPTESTNMWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VK1 }, },
21072   { 15008 /* vptestnmw */, X86::VPTESTNMWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VK1 }, },
21082   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21083   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
21084   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21085   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21086   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21104   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21105   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
21106   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21107   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21108   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21135   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21136   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
21137   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21138   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21139   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21166   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21167   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
21168   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21169   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21170   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21188   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21189   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
21190   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21191   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21192   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21210   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21211   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
21212   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21213   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21214   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21241   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21242   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
21243   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21244   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21245   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21272   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21273   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
21274   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21275   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21276   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21294   { 15108 /* vpxor */, X86::VPXORrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21295   { 15108 /* vpxor */, X86::VPXORYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
21298   { 15114 /* vpxord */, X86::VPXORDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21299   { 15114 /* vpxord */, X86::VPXORDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21300   { 15114 /* vpxord */, X86::VPXORDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21325   { 15121 /* vpxorq */, X86::VPXORQZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21326   { 15121 /* vpxorq */, X86::VPXORQZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21327   { 15121 /* vpxorq */, X86::VPXORQZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21484   { 15182 /* vrcp14sd */, X86::VRCP14SDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21490   { 15191 /* vrcp14ss */, X86::VRCP14SSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21520   { 15218 /* vrcp28sd */, X86::VRCP28SDZr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21529   { 15227 /* vrcp28ss */, X86::VRCP28SSZr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21542   { 15243 /* vrcpss */, X86::VRCPSSr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21766   { 15396 /* vrsqrt14sd */, X86::VRSQRT14SDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21772   { 15407 /* vrsqrt14ss */, X86::VRSQRT14SSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21802   { 15440 /* vrsqrt28sd */, X86::VRSQRT28SDZr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21811   { 15451 /* vrsqrt28ss */, X86::VRSQRT28SSZr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21824   { 15471 /* vrsqrtss */, X86::VRSQRTSSr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
21826   { 15480 /* vscalefpd */, X86::VSCALEFPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21827   { 15480 /* vscalefpd */, X86::VSCALEFPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21828   { 15480 /* vscalefpd */, X86::VSCALEFPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21856   { 15490 /* vscalefps */, X86::VSCALEFPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21857   { 15490 /* vscalefps */, X86::VSCALEFPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
21858   { 15490 /* vscalefps */, X86::VSCALEFPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
21886   { 15500 /* vscalefsd */, X86::VSCALEFSDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
21895   { 15510 /* vscalefss */, X86::VSCALEFSSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22126   { 15764 /* vsqrtsd */, X86::VSQRTSDr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22127   { 15764 /* vsqrtsd */, X86::VSQRTSDZr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22137   { 15772 /* vsqrtss */, X86::VSQRTSSr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22138   { 15772 /* vsqrtss */, X86::VSQRTSSZr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22149   { 15789 /* vsubpd */, X86::VSUBPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22150   { 15789 /* vsubpd */, X86::VSUBPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
22151   { 15789 /* vsubpd */, X86::VSUBPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22152   { 15789 /* vsubpd */, X86::VSUBPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
22153   { 15789 /* vsubpd */, X86::VSUBPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
22183   { 15796 /* vsubps */, X86::VSUBPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22184   { 15796 /* vsubps */, X86::VSUBPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
22185   { 15796 /* vsubps */, X86::VSUBPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22186   { 15796 /* vsubps */, X86::VSUBPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
22187   { 15796 /* vsubps */, X86::VSUBPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
22217   { 15803 /* vsubsd */, X86::VSUBSDrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22218   { 15803 /* vsubsd */, X86::VSUBSDZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22228   { 15810 /* vsubss */, X86::VSUBSSrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22229   { 15810 /* vsubss */, X86::VSUBSSZrr_Int, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22257   { 15851 /* vunpckhpd */, X86::VUNPCKHPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22258   { 15851 /* vunpckhpd */, X86::VUNPCKHPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
22259   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22260   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
22261   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
22288   { 15861 /* vunpckhps */, X86::VUNPCKHPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22289   { 15861 /* vunpckhps */, X86::VUNPCKHPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
22290   { 15861 /* vunpckhps */, X86::VUNPCKHPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22291   { 15861 /* vunpckhps */, X86::VUNPCKHPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
22292   { 15861 /* vunpckhps */, X86::VUNPCKHPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
22319   { 15871 /* vunpcklpd */, X86::VUNPCKLPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22320   { 15871 /* vunpcklpd */, X86::VUNPCKLPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
22321   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22322   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
22323   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
22350   { 15881 /* vunpcklps */, X86::VUNPCKLPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22351   { 15881 /* vunpcklps */, X86::VUNPCKLPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
22352   { 15881 /* vunpcklps */, X86::VUNPCKLPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22353   { 15881 /* vunpcklps */, X86::VUNPCKLPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
22354   { 15881 /* vunpcklps */, X86::VUNPCKLPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
22381   { 15891 /* vxorpd */, X86::VXORPDrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22382   { 15891 /* vxorpd */, X86::VXORPDYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
22383   { 15891 /* vxorpd */, X86::VXORPDZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22384   { 15891 /* vxorpd */, X86::VXORPDZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
22385   { 15891 /* vxorpd */, X86::VXORPDZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
22412   { 15898 /* vxorps */, X86::VXORPSrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
22413   { 15898 /* vxorps */, X86::VXORPSYrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
22414   { 15898 /* vxorps */, X86::VXORPSZ128rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
22415   { 15898 /* vxorps */, X86::VXORPSZ256rr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
22416   { 15898 /* vxorps */, X86::VXORPSZrr, Convert__Reg1_2__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },