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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenAsmMatcher.inc 7970 { 20 /* adcb */, X86::ADC8rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
7976 { 25 /* adcl */, X86::ADC32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
7985 { 30 /* adcq */, X86::ADC64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
7994 { 35 /* adcw */, X86::ADC16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
8007 { 61 /* addb */, X86::ADD8rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
8013 { 66 /* addl */, X86::ADD32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8026 { 83 /* addq */, X86::ADD64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
8043 { 118 /* addw */, X86::ADD16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
8068 { 203 /* andb */, X86::AND8rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
8074 { 208 /* andl */, X86::AND32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8095 { 256 /* andq */, X86::AND64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
8104 { 261 /* andw */, X86::AND16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
8147 { 410 /* blendvpd */, X86::BLENDVPDrr0, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
8151 { 419 /* blendvps */, X86::BLENDVPSrr0, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
8214 { 647 /* btcl */, X86::BTC32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8218 { 652 /* btcq */, X86::BTC64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
8222 { 657 /* btcw */, X86::BTC16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
8235 { 674 /* btrl */, X86::BTR32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8239 { 679 /* btrq */, X86::BTR64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
8243 { 684 /* btrw */, X86::BTR16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
8248 { 693 /* btsl */, X86::BTS32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8252 { 698 /* btsq */, X86::BTS64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
8256 { 703 /* btsw */, X86::BTS16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
8461 { 1525 /* crc32b */, X86::CRC32r32r8, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR32 }, },
8462 { 1525 /* crc32b */, X86::CRC32r64r8, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR64 }, },
8465 { 1532 /* crc32l */, X86::CRC32r32r32, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
8467 { 1539 /* crc32q */, X86::CRC32r64r64, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
8469 { 1546 /* crc32w */, X86::CRC32r32r16, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR32 }, },
8505 { 1693 /* cvtsi2sdl */, X86::CVTSI2SDrr_Int, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32 }, },
8507 { 1703 /* cvtsi2sdq */, X86::CVTSI642SDrr_Int, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32 }, },
8512 { 1722 /* cvtsi2ssl */, X86::CVTSI2SSrr_Int, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32 }, },
8514 { 1732 /* cvtsi2ssq */, X86::CVTSI642SSrr_Int, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32 }, },
8610 { 2076 /* extrq */, X86::EXTRQ, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
8895 { 3237 /* insertq */, X86::INSERTQ, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
9292 { 4735 /* movsd.s */, X86::MOVSDrr_REV, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
9304 { 4786 /* movss.s */, X86::MOVSSrr_REV, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
9406 { 5068 /* orb */, X86::OR8rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
9412 { 5072 /* orl */, X86::OR32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
9425 { 5086 /* orq */, X86::OR64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
9434 { 5090 /* orw */, X86::OR16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
9539 { 5295 /* pblendvb */, X86::PBLENDVBrr0, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10177 { 7078 /* sbbb */, X86::SBB8rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
10183 { 7083 /* sbbl */, X86::SBB32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
10192 { 7088 /* sbbq */, X86::SBB64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
10201 { 7093 /* sbbw */, X86::SBB16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
10271 { 7326 /* sha256rnds2 */, X86::SHA256RNDS2rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10281 { 7352 /* shldl */, X86::SHLD32rrCL, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
10287 { 7358 /* shldq */, X86::SHLD64rrCL, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
10293 { 7364 /* shldw */, X86::SHLD16rrCL, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
10327 { 7416 /* shrdl */, X86::SHRD32rrCL, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
10333 { 7422 /* shrdq */, X86::SHRD64rrCL, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
10339 { 7428 /* shrdw */, X86::SHRD16rrCL, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
10417 { 7688 /* subb */, X86::SUB8rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
10423 { 7693 /* subl */, X86::SUB32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
10436 { 7710 /* subq */, X86::SUB64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
10449 { 7727 /* subw */, X86::SUB16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
22498 { 16196 /* xorb */, X86::XOR8rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
22504 { 16201 /* xorl */, X86::XOR32rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
22517 { 16218 /* xorq */, X86::XOR64rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
22526 { 16223 /* xorw */, X86::XOR16rr, Convert__Reg1_1__Tie0_2_2__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },