reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 8064   { 176 /* aesimc */, X86::AESIMCrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8113   { 266 /* arpl */, X86::ARPL16rr, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_GR16, MCK_GR16 }, },
 8123   { 299 /* blcfilll */, X86::BLCFILL32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8125   { 308 /* blcfillq */, X86::BLCFILL64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8127   { 328 /* blcicl */, X86::BLCIC32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8129   { 335 /* blcicq */, X86::BLCIC64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8131   { 342 /* blcil */, X86::BLCI32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8133   { 348 /* blciq */, X86::BLCI64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8135   { 361 /* blcmskl */, X86::BLCMSK32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8137   { 369 /* blcmskq */, X86::BLCMSK64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8139   { 382 /* blcsl */, X86::BLCS32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8141   { 388 /* blcsq */, X86::BLCS64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8155   { 436 /* blsfilll */, X86::BLSFILL32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8157   { 445 /* blsfillq */, X86::BLSFILL64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8159   { 465 /* blsicl */, X86::BLSIC32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8161   { 472 /* blsicq */, X86::BLSIC64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8163   { 479 /* blsil */, X86::BLSI32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8165   { 485 /* blsiq */, X86::BLSI64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8167   { 498 /* blsmskl */, X86::BLSMSK32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8169   { 506 /* blsmskq */, X86::BLSMSK64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8171   { 519 /* blsrl */, X86::BLSR32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8173   { 525 /* blsrq */, X86::BLSR64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8175   { 531 /* bndcl */, X86::BNDCL32rr, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_GR32, MCK_BNDR }, },
 8176   { 531 /* bndcl */, X86::BNDCL64rr, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_GR64, MCK_BNDR }, },
 8179   { 537 /* bndcn */, X86::BNDCN32rr, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_GR32, MCK_BNDR }, },
 8180   { 537 /* bndcn */, X86::BNDCN64rr, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_GR64, MCK_BNDR }, },
 8183   { 543 /* bndcu */, X86::BNDCU32rr, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_GR32, MCK_BNDR }, },
 8184   { 543 /* bndcu */, X86::BNDCU64rr, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_GR64, MCK_BNDR }, },
 8190   { 562 /* bndmov */, X86::BNDMOVrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_BNDR, MCK_BNDR }, },
 8198   { 586 /* bsfl */, X86::BSF32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8200   { 591 /* bsfq */, X86::BSF64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8202   { 596 /* bsfw */, X86::BSF16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 8204   { 605 /* bsrl */, X86::BSR32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8206   { 610 /* bsrq */, X86::BSR64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8208   { 615 /* bsrw */, X86::BSR16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 8226   { 662 /* btl */, X86::BT32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8230   { 666 /* btq */, X86::BT64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8260   { 708 /* btw */, X86::BT16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 8400   { 1352 /* cmpb */, X86::CMP8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
 8406   { 1357 /* cmpl */, X86::CMP32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8419   { 1374 /* cmpq */, X86::CMP64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8436   { 1420 /* cmpw */, X86::CMP16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 8447   { 1454 /* cmpxchgb */, X86::CMPXCHG8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
 8449   { 1463 /* cmpxchgl */, X86::CMPXCHG32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 8451   { 1472 /* cmpxchgq */, X86::CMPXCHG64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 8453   { 1481 /* cmpxchgw */, X86::CMPXCHG16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 8455   { 1490 /* comisd */, X86::COMISDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8457   { 1497 /* comiss */, X86::COMISSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8472   { 1556 /* cvtdq2pd */, X86::CVTDQ2PDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8474   { 1565 /* cvtdq2ps */, X86::CVTDQ2PSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8476   { 1574 /* cvtpd2dq */, X86::CVTPD2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8478   { 1583 /* cvtpd2pi */, X86::MMX_CVTPD2PIirr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR64 }, },
 8480   { 1592 /* cvtpd2ps */, X86::CVTPD2PSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8482   { 1601 /* cvtpi2pd */, X86::MMX_CVTPI2PDirr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_FR32 }, },
 8486   { 1619 /* cvtps2dq */, X86::CVTPS2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8488   { 1628 /* cvtps2pd */, X86::CVTPS2PDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8490   { 1637 /* cvtps2pi */, X86::MMX_CVTPS2PIirr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR64 }, },
 8492   { 1646 /* cvtsd2si */, X86::CVTSD2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
 8493   { 1646 /* cvtsd2si */, X86::CVTSD2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 8496   { 1655 /* cvtsd2sil */, X86::CVTSD2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
 8498   { 1665 /* cvtsd2siq */, X86::CVTSD2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 8518   { 1751 /* cvtss2si */, X86::CVTSS2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
 8519   { 1751 /* cvtss2si */, X86::CVTSS2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 8522   { 1760 /* cvtss2sil */, X86::CVTSS2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
 8524   { 1770 /* cvtss2siq */, X86::CVTSS2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 8526   { 1780 /* cvttpd2dq */, X86::CVTTPD2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8528   { 1790 /* cvttpd2pi */, X86::MMX_CVTTPD2PIirr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR64 }, },
 8530   { 1800 /* cvttps2dq */, X86::CVTTPS2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 8532   { 1810 /* cvttps2pi */, X86::MMX_CVTTPS2PIirr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR64 }, },
 8534   { 1820 /* cvttsd2si */, X86::CVTTSD2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
 8535   { 1820 /* cvttsd2si */, X86::CVTTSD2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 8538   { 1830 /* cvttsd2sil */, X86::CVTTSD2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
 8540   { 1841 /* cvttsd2siq */, X86::CVTTSD2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 8542   { 1852 /* cvttss2si */, X86::CVTTSS2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
 8543   { 1852 /* cvttss2si */, X86::CVTTSS2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 8546   { 1862 /* cvttss2sil */, X86::CVTTSS2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
 8548   { 1873 /* cvttss2siq */, X86::CVTTSS2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 8964   { 3513 /* kmovb */, X86::KMOVBkk, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8965   { 3513 /* kmovb */, X86::KMOVBrk, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_GR32 }, },
 8967   { 3513 /* kmovb */, X86::KMOVBkr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VK1 }, },
 8969   { 3519 /* kmovd */, X86::KMOVDkk, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8970   { 3519 /* kmovd */, X86::KMOVDrk, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_GR32 }, },
 8972   { 3519 /* kmovd */, X86::KMOVDkr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VK1 }, },
 8974   { 3525 /* kmovq */, X86::KMOVQkk, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8975   { 3525 /* kmovq */, X86::KMOVQrk, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_GR64 }, },
 8977   { 3525 /* kmovq */, X86::KMOVQkr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_VK1 }, },
 8979   { 3531 /* kmovw */, X86::KMOVWkk, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8980   { 3531 /* kmovw */, X86::KMOVWrk, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_GR32 }, },
 8982   { 3531 /* kmovw */, X86::KMOVWkr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VK1 }, },
 8984   { 3537 /* knotb */, X86::KNOTBrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8985   { 3543 /* knotd */, X86::KNOTDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8986   { 3549 /* knotq */, X86::KNOTQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8987   { 3555 /* knotw */, X86::KNOTWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8991   { 3576 /* kortestb */, X86::KORTESTBrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8992   { 3585 /* kortestd */, X86::KORTESTDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8993   { 3594 /* kortestq */, X86::KORTESTQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 8994   { 3603 /* kortestw */, X86::KORTESTWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 9004   { 3689 /* ktestb */, X86::KTESTBrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 9005   { 3696 /* ktestd */, X86::KTESTDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 9006   { 3703 /* ktestq */, X86::KTESTQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 9007   { 3710 /* ktestw */, X86::KTESTWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VK1 }, },
 9020   { 3805 /* larl */, X86::LAR32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 9022   { 3810 /* larq */, X86::LAR64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR64 }, },
 9024   { 3815 /* larw */, X86::LAR16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 9097   { 4149 /* lsll */, X86::LSL32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 9099   { 4154 /* lslq */, X86::LSL64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR64 }, },
 9101   { 4159 /* lslw */, X86::LSL16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 9116   { 4212 /* lzcntl */, X86::LZCNT32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 9118   { 4219 /* lzcntq */, X86::LZCNT64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 9120   { 4226 /* lzcntw */, X86::LZCNT16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 9122   { 4233 /* maskmovdqu */, X86::MASKMOVDQU, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_FR32, MCK_FR32 }, },
 9123   { 4233 /* maskmovdqu */, X86::MASKMOVDQU64, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_FR32, MCK_FR32 }, },
 9124   { 4244 /* maskmovq */, X86::MMX_MASKMOVQ, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_VR64, MCK_VR64 }, },
 9125   { 4244 /* maskmovq */, X86::MMX_MASKMOVQ64, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_VR64, MCK_VR64 }, },
 9152   { 4337 /* mov.s */, X86::MOV16rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 9153   { 4337 /* mov.s */, X86::MOV32rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 9154   { 4337 /* mov.s */, X86::MOV64rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 9155   { 4337 /* mov.s */, X86::MOV8rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
 9165   { 4382 /* movapd */, X86::MOVAPDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9168   { 4389 /* movapd.s */, X86::MOVAPDrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9169   { 4398 /* movaps */, X86::MOVAPSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9172   { 4405 /* movaps.s */, X86::MOVAPSrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9175   { 4414 /* movb */, X86::MOV8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
 9182   { 4419 /* movb.s */, X86::MOV8rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
 9189   { 4453 /* movd */, X86::MMX_MOVD64grr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_GR32 }, },
 9190   { 4453 /* movd */, X86::MMX_MOVD64from64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_GR64 }, },
 9192   { 4453 /* movd */, X86::MOVPDI2DIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
 9193   { 4453 /* movd */, X86::MOVPQIto64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 9195   { 4453 /* movd */, X86::MMX_MOVD64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VR64 }, },
 9196   { 4453 /* movd */, X86::MOVDI2PDIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32 }, },
 9197   { 4453 /* movd */, X86::MMX_MOVD64to64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_VR64 }, },
 9198   { 4453 /* movd */, X86::MOV64toPQIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32 }, },
 9201   { 4458 /* movddup */, X86::MOVDDUPrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9208   { 4484 /* movdq2q */, X86::MMX_MOVDQ2Qrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR64 }, },
 9209   { 4492 /* movdqa */, X86::MOVDQArr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9212   { 4499 /* movdqa.s */, X86::MOVDQArr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9213   { 4508 /* movdqu */, X86::MOVDQUrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9216   { 4515 /* movdqu.s */, X86::MOVDQUrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9224   { 4546 /* movl */, X86::MOV32rs, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_SEGMENT_REG, MCK_GR32 }, },
 9225   { 4546 /* movl */, X86::MOV32rc, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_CONTROL_REG, MCK_GR32 }, },
 9226   { 4546 /* movl */, X86::MOV32rd, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_DEBUG_REG, MCK_GR32 }, },
 9227   { 4546 /* movl */, X86::MOV32sr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_SEGMENT_REG }, },
 9228   { 4546 /* movl */, X86::MOV32cr, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_GR32, MCK_CONTROL_REG }, },
 9229   { 4546 /* movl */, X86::MOV32dr, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_GR32, MCK_DEBUG_REG }, },
 9230   { 4546 /* movl */, X86::MOV32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 9237   { 4551 /* movl.s */, X86::MOV32rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 9255   { 4677 /* movq */, X86::MOV64rs, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_SEGMENT_REG, MCK_GR64 }, },
 9256   { 4677 /* movq */, X86::MMX_MOVQ64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9257   { 4677 /* movq */, X86::MMX_MOVD64from64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_GR64 }, },
 9259   { 4677 /* movq */, X86::MOV64rc, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_CONTROL_REG, MCK_GR64 }, },
 9260   { 4677 /* movq */, X86::MOV64rd, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_DEBUG_REG, MCK_GR64 }, },
 9261   { 4677 /* movq */, X86::MOVZPQILo2PQIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9262   { 4677 /* movq */, X86::MOVPQIto64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
 9264   { 4677 /* movq */, X86::MOV64sr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_SEGMENT_REG }, },
 9265   { 4677 /* movq */, X86::MMX_MOVD64to64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_VR64 }, },
 9266   { 4677 /* movq */, X86::MOV64cr, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_GR64, MCK_CONTROL_REG }, },
 9267   { 4677 /* movq */, X86::MOV64dr, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_GR64, MCK_DEBUG_REG }, },
 9268   { 4677 /* movq */, X86::MOV64toPQIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32 }, },
 9269   { 4677 /* movq */, X86::MOV64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 9278   { 4682 /* movq.s */, X86::MMX_MOVQ64rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9279   { 4682 /* movq.s */, X86::MOVPQI2QIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9280   { 4682 /* movq.s */, X86::MOV64rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 9281   { 4689 /* movq2dq */, X86::MMX_MOVQ2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_FR32 }, },
 9283   { 4708 /* movsbl */, X86::MOVSX32rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR32 }, },
 9285   { 4715 /* movsbq */, X86::MOVSX64rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR64 }, },
 9287   { 4722 /* movsbw */, X86::MOVSX16rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR16 }, },
 9293   { 4743 /* movshdup */, X86::MOVSHDUPrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9296   { 4758 /* movsldup */, X86::MOVSLDUPrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9298   { 4767 /* movslq */, X86::MOVSX64rr32, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_GR32, MCK_GR64 }, },
 9306   { 4800 /* movswl */, X86::MOVSX32rr16, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR32 }, },
 9308   { 4807 /* movswq */, X86::MOVSX64rr16, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR64 }, },
 9310   { 4814 /* movsx */, X86::MOVSX32rr16, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR32 }, },
 9311   { 4814 /* movsx */, X86::MOVSX64rr16, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR64 }, },
 9312   { 4814 /* movsx */, X86::MOVSX64rr32, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR64 }, },
 9313   { 4814 /* movsx */, X86::MOVSX16rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR16 }, },
 9314   { 4814 /* movsx */, X86::MOVSX32rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR32 }, },
 9315   { 4814 /* movsx */, X86::MOVSX64rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR64 }, },
 9317   { 4827 /* movupd */, X86::MOVUPDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9320   { 4834 /* movupd.s */, X86::MOVUPDrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9321   { 4843 /* movups */, X86::MOVUPSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9324   { 4850 /* movups.s */, X86::MOVUPSrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9327   { 4859 /* movw */, X86::MOV16rs, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_SEGMENT_REG, MCK_GR16 }, },
 9329   { 4859 /* movw */, X86::MOV16sr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_SEGMENT_REG }, },
 9330   { 4859 /* movw */, X86::MOV16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 9338   { 4864 /* movw.s */, X86::MOV16rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 9339   { 4871 /* movzbl */, X86::MOVZX32rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR32 }, },
 9341   { 4878 /* movzbq */, X86::MOVZX64rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR64 }, },
 9343   { 4885 /* movzbw */, X86::MOVZX16rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR16 }, },
 9345   { 4892 /* movzwl */, X86::MOVZX32rr16, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR32 }, },
 9347   { 4899 /* movzwq */, X86::MOVZX64rr16, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR64 }, },
 9349   { 4906 /* movzx */, X86::MOVZX32rr16, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR32 }, },
 9350   { 4906 /* movzx */, X86::MOVZX64rr16, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR64 }, },
 9351   { 4906 /* movzx */, X86::MOVZX16rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR16 }, },
 9352   { 4906 /* movzx */, X86::MOVZX32rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR32 }, },
 9353   { 4906 /* movzx */, X86::MOVZX64rr8, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR64 }, },
 9458   { 5142 /* pabsb */, X86::MMX_PABSBrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9459   { 5142 /* pabsb */, X86::PABSBrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9462   { 5148 /* pabsd */, X86::MMX_PABSDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9463   { 5148 /* pabsd */, X86::PABSDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9466   { 5154 /* pabsw */, X86::MMX_PABSWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9467   { 5154 /* pabsw */, X86::PABSWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9609   { 5548 /* pf2id */, X86::PF2IDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9611   { 5554 /* pf2iw */, X86::PF2IWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9633   { 5629 /* pfrcp */, X86::PFRCPrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9641   { 5662 /* pfrsqrt */, X86::PFRSQRTrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9659   { 5705 /* phminposuw */, X86::PHMINPOSUWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9673   { 5738 /* pi2fd */, X86::PI2FDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9675   { 5744 /* pi2fw */, X86::PI2FWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9729   { 5889 /* pmovsxbd */, X86::PMOVSXBDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9731   { 5898 /* pmovsxbq */, X86::PMOVSXBQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9733   { 5907 /* pmovsxbw */, X86::PMOVSXBWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9735   { 5916 /* pmovsxdq */, X86::PMOVSXDQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9737   { 5925 /* pmovsxwd */, X86::PMOVSXWDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9739   { 5934 /* pmovsxwq */, X86::PMOVSXWQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9741   { 5943 /* pmovzxbd */, X86::PMOVZXBDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9743   { 5952 /* pmovzxbq */, X86::PMOVZXBQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9745   { 5961 /* pmovzxbw */, X86::PMOVZXBWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9747   { 5970 /* pmovzxdq */, X86::PMOVZXDQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9749   { 5979 /* pmovzxwd */, X86::PMOVZXWDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9751   { 5988 /* pmovzxwq */, X86::PMOVZXWQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
 9781   { 6081 /* popcntl */, X86::POPCNT32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
 9783   { 6089 /* popcntq */, X86::POPCNT64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
 9785   { 6097 /* popcntw */, X86::POPCNT16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
 9929   { 6410 /* pswapd */, X86::PSWAPDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR64, MCK_VR64 }, },
 9931   { 6417 /* ptest */, X86::PTESTrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10024   { 6631 /* rcpps */, X86::RCPPSr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10141   { 6986 /* rsqrtps */, X86::RSQRTPSr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10386   { 7569 /* sqrtpd */, X86::SQRTPDr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10388   { 7576 /* sqrtps */, X86::SQRTPSr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10465   { 7812 /* t1mskcl */, X86::T1MSKC32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
10467   { 7820 /* t1mskcq */, X86::T1MSKC64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
10469   { 7833 /* testb */, X86::TEST8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
10475   { 7839 /* testl */, X86::TEST32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
10481   { 7845 /* testq */, X86::TEST64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
10487   { 7851 /* testw */, X86::TEST16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
10494   { 7870 /* tzcntl */, X86::TZCNT32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
10496   { 7877 /* tzcntq */, X86::TZCNT64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
10498   { 7884 /* tzcntw */, X86::TZCNT16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
10500   { 7897 /* tzmskl */, X86::TZMSK32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
10502   { 7904 /* tzmskq */, X86::TZMSK64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_GR64 }, },
10504   { 7911 /* ucomisd */, X86::UCOMISDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10506   { 7919 /* ucomiss */, X86::UCOMISSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10672   { 8118 /* vaesimc */, X86::VAESIMCrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
10925   { 8262 /* vbroadcastf32x2 */, X86::VBROADCASTF32X2Z256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
10926   { 8262 /* vbroadcastf32x2 */, X86::VBROADCASTF32X2Zr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
10956   { 8357 /* vbroadcasti32x2 */, X86::VBROADCASTI32X2Z128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
10957   { 8357 /* vbroadcasti32x2 */, X86::VBROADCASTI32X2Z256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
10958   { 8357 /* vbroadcasti32x2 */, X86::VBROADCASTI32X2Zr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
10992   { 8437 /* vbroadcastsd */, X86::VBROADCASTSDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
10993   { 8437 /* vbroadcastsd */, X86::VBROADCASTSDZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
10994   { 8437 /* vbroadcastsd */, X86::VBROADCASTSDZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
11006   { 8450 /* vbroadcastss */, X86::VBROADCASTSSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11007   { 8450 /* vbroadcastss */, X86::VBROADCASTSSYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
11008   { 8450 /* vbroadcastss */, X86::VBROADCASTSSZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11009   { 8450 /* vbroadcastss */, X86::VBROADCASTSSZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
11010   { 8450 /* vbroadcastss */, X86::VBROADCASTSSZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
11092   { 8491 /* vcomisd */, X86::VCOMISDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11093   { 8491 /* vcomisd */, X86::VCOMISDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11097   { 8499 /* vcomiss */, X86::VCOMISSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11098   { 8499 /* vcomiss */, X86::VCOMISSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11102   { 8507 /* vcompresspd */, X86::VCOMPRESSPDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11104   { 8507 /* vcompresspd */, X86::VCOMPRESSPDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11106   { 8507 /* vcompresspd */, X86::VCOMPRESSPDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11117   { 8519 /* vcompressps */, X86::VCOMPRESSPSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11119   { 8519 /* vcompressps */, X86::VCOMPRESSPSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11121   { 8519 /* vcompressps */, X86::VCOMPRESSPSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11132   { 8531 /* vcvtdq2pd */, X86::VCVTDQ2PDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11133   { 8531 /* vcvtdq2pd */, X86::VCVTDQ2PDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
11134   { 8531 /* vcvtdq2pd */, X86::VCVTDQ2PDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11135   { 8531 /* vcvtdq2pd */, X86::VCVTDQ2PDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
11136   { 8531 /* vcvtdq2pd */, X86::VCVTDQ2PDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
11163   { 8541 /* vcvtdq2ps */, X86::VCVTDQ2PSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11164   { 8541 /* vcvtdq2ps */, X86::VCVTDQ2PSYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
11165   { 8541 /* vcvtdq2ps */, X86::VCVTDQ2PSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11166   { 8541 /* vcvtdq2ps */, X86::VCVTDQ2PSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11167   { 8541 /* vcvtdq2ps */, X86::VCVTDQ2PSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11224   { 8566 /* vcvtneps2bf16 */, X86::VCVTNEPS2BF16Z128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11225   { 8566 /* vcvtneps2bf16 */, X86::VCVTNEPS2BF16Z256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11226   { 8566 /* vcvtneps2bf16 */, X86::VCVTNEPS2BF16Zrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
11245   { 8580 /* vcvtneps2bf16x */, X86::VCVTNEPS2BF16Z128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11249   { 8595 /* vcvtneps2bf16y */, X86::VCVTNEPS2BF16Z256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11253   { 8610 /* vcvtpd2dq */, X86::VCVTPD2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11254   { 8610 /* vcvtpd2dq */, X86::VCVTPD2DQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_FR32 }, },
11255   { 8610 /* vcvtpd2dq */, X86::VCVTPD2DQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11256   { 8610 /* vcvtpd2dq */, X86::VCVTPD2DQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11257   { 8610 /* vcvtpd2dq */, X86::VCVTPD2DQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
11279   { 8620 /* vcvtpd2dqx */, X86::VCVTPD2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11280   { 8620 /* vcvtpd2dqx */, X86::VCVTPD2DQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11290   { 8631 /* vcvtpd2dqy */, X86::VCVTPD2DQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_FR32 }, },
11291   { 8631 /* vcvtpd2dqy */, X86::VCVTPD2DQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11301   { 8642 /* vcvtpd2ps */, X86::VCVTPD2PSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11302   { 8642 /* vcvtpd2ps */, X86::VCVTPD2PSYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_FR32 }, },
11303   { 8642 /* vcvtpd2ps */, X86::VCVTPD2PSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11304   { 8642 /* vcvtpd2ps */, X86::VCVTPD2PSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11305   { 8642 /* vcvtpd2ps */, X86::VCVTPD2PSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
11327   { 8652 /* vcvtpd2psx */, X86::VCVTPD2PSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11328   { 8652 /* vcvtpd2psx */, X86::VCVTPD2PSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11338   { 8663 /* vcvtpd2psy */, X86::VCVTPD2PSYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_FR32 }, },
11339   { 8663 /* vcvtpd2psy */, X86::VCVTPD2PSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11349   { 8674 /* vcvtpd2qq */, X86::VCVTPD2QQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11350   { 8674 /* vcvtpd2qq */, X86::VCVTPD2QQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11351   { 8674 /* vcvtpd2qq */, X86::VCVTPD2QQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11379   { 8684 /* vcvtpd2udq */, X86::VCVTPD2UDQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11380   { 8684 /* vcvtpd2udq */, X86::VCVTPD2UDQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11381   { 8684 /* vcvtpd2udq */, X86::VCVTPD2UDQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
11403   { 8695 /* vcvtpd2udqx */, X86::VCVTPD2UDQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11412   { 8707 /* vcvtpd2udqy */, X86::VCVTPD2UDQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11421   { 8719 /* vcvtpd2uqq */, X86::VCVTPD2UQQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11422   { 8719 /* vcvtpd2uqq */, X86::VCVTPD2UQQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11423   { 8719 /* vcvtpd2uqq */, X86::VCVTPD2UQQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11451   { 8730 /* vcvtph2ps */, X86::VCVTPH2PSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11452   { 8730 /* vcvtph2ps */, X86::VCVTPH2PSYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
11453   { 8730 /* vcvtph2ps */, X86::VCVTPH2PSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11454   { 8730 /* vcvtph2ps */, X86::VCVTPH2PSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
11455   { 8730 /* vcvtph2ps */, X86::VCVTPH2PSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
11476   { 8740 /* vcvtps2dq */, X86::VCVTPS2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11477   { 8740 /* vcvtps2dq */, X86::VCVTPS2DQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
11478   { 8740 /* vcvtps2dq */, X86::VCVTPS2DQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11479   { 8740 /* vcvtps2dq */, X86::VCVTPS2DQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11480   { 8740 /* vcvtps2dq */, X86::VCVTPS2DQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11510   { 8750 /* vcvtps2pd */, X86::VCVTPS2PDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11511   { 8750 /* vcvtps2pd */, X86::VCVTPS2PDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
11512   { 8750 /* vcvtps2pd */, X86::VCVTPS2PDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11513   { 8750 /* vcvtps2pd */, X86::VCVTPS2PDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
11514   { 8750 /* vcvtps2pd */, X86::VCVTPS2PDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
11566   { 8770 /* vcvtps2qq */, X86::VCVTPS2QQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11567   { 8770 /* vcvtps2qq */, X86::VCVTPS2QQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
11568   { 8770 /* vcvtps2qq */, X86::VCVTPS2QQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
11596   { 8780 /* vcvtps2udq */, X86::VCVTPS2UDQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11597   { 8780 /* vcvtps2udq */, X86::VCVTPS2UDQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11598   { 8780 /* vcvtps2udq */, X86::VCVTPS2UDQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11626   { 8791 /* vcvtps2uqq */, X86::VCVTPS2UQQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11627   { 8791 /* vcvtps2uqq */, X86::VCVTPS2UQQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
11628   { 8791 /* vcvtps2uqq */, X86::VCVTPS2UQQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
11656   { 8802 /* vcvtqq2pd */, X86::VCVTQQ2PDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11657   { 8802 /* vcvtqq2pd */, X86::VCVTQQ2PDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11658   { 8802 /* vcvtqq2pd */, X86::VCVTQQ2PDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11686   { 8812 /* vcvtqq2ps */, X86::VCVTQQ2PSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11687   { 8812 /* vcvtqq2ps */, X86::VCVTQQ2PSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11688   { 8812 /* vcvtqq2ps */, X86::VCVTQQ2PSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
11710   { 8822 /* vcvtqq2psx */, X86::VCVTQQ2PSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11719   { 8833 /* vcvtqq2psy */, X86::VCVTQQ2PSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11728   { 8844 /* vcvtsd2si */, X86::VCVTSD2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
11729   { 8844 /* vcvtsd2si */, X86::VCVTSD2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
11730   { 8844 /* vcvtsd2si */, X86::VCVTSD2SIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
11731   { 8844 /* vcvtsd2si */, X86::VCVTSD2SI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
11738   { 8854 /* vcvtsd2sil */, X86::VCVTSD2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
11739   { 8854 /* vcvtsd2sil */, X86::VCVTSD2SIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
11743   { 8865 /* vcvtsd2siq */, X86::VCVTSD2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
11744   { 8865 /* vcvtsd2siq */, X86::VCVTSD2SI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
11759   { 8886 /* vcvtsd2usi */, X86::VCVTSD2USIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
11760   { 8886 /* vcvtsd2usi */, X86::VCVTSD2USI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
11765   { 8897 /* vcvtsd2usil */, X86::VCVTSD2USIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
11768   { 8909 /* vcvtsd2usiq */, X86::VCVTSD2USI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
11816   { 8995 /* vcvtss2si */, X86::VCVTSS2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
11817   { 8995 /* vcvtss2si */, X86::VCVTSS2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
11818   { 8995 /* vcvtss2si */, X86::VCVTSS2SIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
11819   { 8995 /* vcvtss2si */, X86::VCVTSS2SI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
11826   { 9005 /* vcvtss2sil */, X86::VCVTSS2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
11827   { 9005 /* vcvtss2sil */, X86::VCVTSS2SIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
11831   { 9016 /* vcvtss2siq */, X86::VCVTSS2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
11832   { 9016 /* vcvtss2siq */, X86::VCVTSS2SI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
11836   { 9027 /* vcvtss2usi */, X86::VCVTSS2USIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
11837   { 9027 /* vcvtss2usi */, X86::VCVTSS2USI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
11842   { 9038 /* vcvtss2usil */, X86::VCVTSS2USIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
11845   { 9050 /* vcvtss2usiq */, X86::VCVTSS2USI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
11848   { 9062 /* vcvttpd2dq */, X86::VCVTTPD2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11849   { 9062 /* vcvttpd2dq */, X86::VCVTTPD2DQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_FR32 }, },
11850   { 9062 /* vcvttpd2dq */, X86::VCVTTPD2DQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11851   { 9062 /* vcvttpd2dq */, X86::VCVTTPD2DQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11852   { 9062 /* vcvttpd2dq */, X86::VCVTTPD2DQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
11874   { 9073 /* vcvttpd2dqx */, X86::VCVTTPD2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11875   { 9073 /* vcvttpd2dqx */, X86::VCVTTPD2DQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11885   { 9085 /* vcvttpd2dqy */, X86::VCVTTPD2DQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_FR32 }, },
11886   { 9085 /* vcvttpd2dqy */, X86::VCVTTPD2DQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11896   { 9097 /* vcvttpd2qq */, X86::VCVTTPD2QQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11897   { 9097 /* vcvttpd2qq */, X86::VCVTTPD2QQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11898   { 9097 /* vcvttpd2qq */, X86::VCVTTPD2QQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11926   { 9108 /* vcvttpd2udq */, X86::VCVTTPD2UDQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11927   { 9108 /* vcvttpd2udq */, X86::VCVTTPD2UDQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11928   { 9108 /* vcvttpd2udq */, X86::VCVTTPD2UDQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
11950   { 9120 /* vcvttpd2udqx */, X86::VCVTTPD2UDQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11959   { 9133 /* vcvttpd2udqy */, X86::VCVTTPD2UDQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
11968   { 9146 /* vcvttpd2uqq */, X86::VCVTTPD2UQQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
11969   { 9146 /* vcvttpd2uqq */, X86::VCVTTPD2UQQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
11970   { 9146 /* vcvttpd2uqq */, X86::VCVTTPD2UQQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
11998   { 9158 /* vcvttps2dq */, X86::VCVTTPS2DQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
11999   { 9158 /* vcvttps2dq */, X86::VCVTTPS2DQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
12000   { 9158 /* vcvttps2dq */, X86::VCVTTPS2DQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12001   { 9158 /* vcvttps2dq */, X86::VCVTTPS2DQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
12002   { 9158 /* vcvttps2dq */, X86::VCVTTPS2DQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
12032   { 9169 /* vcvttps2qq */, X86::VCVTTPS2QQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12033   { 9169 /* vcvttps2qq */, X86::VCVTTPS2QQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
12034   { 9169 /* vcvttps2qq */, X86::VCVTTPS2QQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
12062   { 9180 /* vcvttps2udq */, X86::VCVTTPS2UDQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12063   { 9180 /* vcvttps2udq */, X86::VCVTTPS2UDQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
12064   { 9180 /* vcvttps2udq */, X86::VCVTTPS2UDQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
12092   { 9192 /* vcvttps2uqq */, X86::VCVTTPS2UQQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12093   { 9192 /* vcvttps2uqq */, X86::VCVTTPS2UQQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
12094   { 9192 /* vcvttps2uqq */, X86::VCVTTPS2UQQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
12122   { 9204 /* vcvttsd2si */, X86::VCVTTSD2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
12123   { 9204 /* vcvttsd2si */, X86::VCVTTSD2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
12124   { 9204 /* vcvttsd2si */, X86::VCVTTSD2SIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
12125   { 9204 /* vcvttsd2si */, X86::VCVTTSD2SI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
12132   { 9215 /* vcvttsd2sil */, X86::VCVTTSD2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
12133   { 9215 /* vcvttsd2sil */, X86::VCVTTSD2SIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
12137   { 9227 /* vcvttsd2siq */, X86::VCVTTSD2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
12138   { 9227 /* vcvttsd2siq */, X86::VCVTTSD2SI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
12142   { 9239 /* vcvttsd2usi */, X86::VCVTTSD2USIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
12143   { 9239 /* vcvttsd2usi */, X86::VCVTTSD2USI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
12148   { 9251 /* vcvttsd2usil */, X86::VCVTTSD2USIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
12151   { 9264 /* vcvttsd2usiq */, X86::VCVTTSD2USI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
12154   { 9277 /* vcvttss2si */, X86::VCVTTSS2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
12155   { 9277 /* vcvttss2si */, X86::VCVTTSS2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
12156   { 9277 /* vcvttss2si */, X86::VCVTTSS2SIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
12157   { 9277 /* vcvttss2si */, X86::VCVTTSS2SI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
12164   { 9288 /* vcvttss2sil */, X86::VCVTTSS2SIrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
12165   { 9288 /* vcvttss2sil */, X86::VCVTTSS2SIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
12169   { 9300 /* vcvttss2siq */, X86::VCVTTSS2SI64rr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
12170   { 9300 /* vcvttss2siq */, X86::VCVTTSS2SI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
12174   { 9312 /* vcvttss2usi */, X86::VCVTTSS2USIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
12175   { 9312 /* vcvttss2usi */, X86::VCVTTSS2USI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
12180   { 9324 /* vcvttss2usil */, X86::VCVTTSS2USIZrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
12183   { 9337 /* vcvttss2usiq */, X86::VCVTTSS2USI64Zrr_Int, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
12186   { 9350 /* vcvtudq2pd */, X86::VCVTUDQ2PDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12187   { 9350 /* vcvtudq2pd */, X86::VCVTUDQ2PDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
12188   { 9350 /* vcvtudq2pd */, X86::VCVTUDQ2PDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
12213   { 9361 /* vcvtudq2ps */, X86::VCVTUDQ2PSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12214   { 9361 /* vcvtudq2ps */, X86::VCVTUDQ2PSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
12215   { 9361 /* vcvtudq2ps */, X86::VCVTUDQ2PSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
12243   { 9372 /* vcvtuqq2pd */, X86::VCVTUQQ2PDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12244   { 9372 /* vcvtuqq2pd */, X86::VCVTUQQ2PDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
12245   { 9372 /* vcvtuqq2pd */, X86::VCVTUQQ2PDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
12273   { 9383 /* vcvtuqq2ps */, X86::VCVTUQQ2PSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12274   { 9383 /* vcvtuqq2ps */, X86::VCVTUQQ2PSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
12275   { 9383 /* vcvtuqq2ps */, X86::VCVTUQQ2PSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
12297   { 9394 /* vcvtuqq2psx */, X86::VCVTUQQ2PSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12306   { 9406 /* vcvtuqq2psy */, X86::VCVTUQQ2PSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
12480   { 9558 /* vexp2pd */, X86::VEXP2PDZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
12492   { 9566 /* vexp2ps */, X86::VEXP2PSZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
12504   { 9574 /* vexpandpd */, X86::VEXPANDPDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12505   { 9574 /* vexpandpd */, X86::VEXPANDPDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
12506   { 9574 /* vexpandpd */, X86::VEXPANDPDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
12522   { 9584 /* vexpandps */, X86::VEXPANDPSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
12523   { 9584 /* vexpandps */, X86::VEXPANDPSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
12524   { 9584 /* vexpandps */, X86::VEXPANDPSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
14338   { 10887 /* vfrczpd */, X86::VFRCZPDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
14339   { 10887 /* vfrczpd */, X86::VFRCZPDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
14342   { 10895 /* vfrczps */, X86::VFRCZPSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
14343   { 10895 /* vfrczps */, X86::VFRCZPSYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
14346   { 10903 /* vfrczsd */, X86::VFRCZSDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
14348   { 10911 /* vfrczss */, X86::VFRCZSSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
14378   { 11075 /* vgetexppd */, X86::VGETEXPPDZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
14379   { 11075 /* vgetexppd */, X86::VGETEXPPDZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
14380   { 11075 /* vgetexppd */, X86::VGETEXPPDZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
14408   { 11085 /* vgetexpps */, X86::VGETEXPPSZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
14409   { 11085 /* vgetexpps */, X86::VGETEXPPSZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
14410   { 11085 /* vgetexpps */, X86::VGETEXPPSZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
14717   { 11389 /* vmaskmovdqu */, X86::VMASKMOVDQU, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_FR32, MCK_FR32 }, },
14718   { 11389 /* vmaskmovdqu */, X86::VMASKMOVDQU64, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_FR32, MCK_FR32 }, },
14914   { 11525 /* vmovapd */, X86::VMOVAPDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
14916   { 11525 /* vmovapd */, X86::VMOVAPDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
14918   { 11525 /* vmovapd */, X86::VMOVAPDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
14920   { 11525 /* vmovapd */, X86::VMOVAPDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
14922   { 11525 /* vmovapd */, X86::VMOVAPDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
14944   { 11533 /* vmovapd.s */, X86::VMOVAPDrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
14945   { 11533 /* vmovapd.s */, X86::VMOVAPDYrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
14946   { 11533 /* vmovapd.s */, X86::VMOVAPDZ128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
14947   { 11533 /* vmovapd.s */, X86::VMOVAPDZ256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
14948   { 11533 /* vmovapd.s */, X86::VMOVAPDZrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
14955   { 11543 /* vmovaps */, X86::VMOVAPSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
14957   { 11543 /* vmovaps */, X86::VMOVAPSYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
14959   { 11543 /* vmovaps */, X86::VMOVAPSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
14961   { 11543 /* vmovaps */, X86::VMOVAPSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
14963   { 11543 /* vmovaps */, X86::VMOVAPSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
14985   { 11551 /* vmovaps.s */, X86::VMOVAPSrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
14986   { 11551 /* vmovaps.s */, X86::VMOVAPSYrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
14987   { 11551 /* vmovaps.s */, X86::VMOVAPSZ128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
14988   { 11551 /* vmovaps.s */, X86::VMOVAPSZ256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
14989   { 11551 /* vmovaps.s */, X86::VMOVAPSZrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
14996   { 11561 /* vmovd */, X86::VMOVPDI2DIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR32 }, },
14997   { 11561 /* vmovd */, X86::VMOVPQIto64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
14999   { 11561 /* vmovd */, X86::VMOVDI2PDIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32 }, },
15000   { 11561 /* vmovd */, X86::VMOVDI2PDIZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X }, },
15001   { 11561 /* vmovd */, X86::VMOV64toPQIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32 }, },
15002   { 11561 /* vmovd */, X86::VMOV64toPQIZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X }, },
15003   { 11561 /* vmovd */, X86::VMOVPDI2DIZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR32 }, },
15004   { 11561 /* vmovd */, X86::VMOVPQIto64Zrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
15008   { 11567 /* vmovddup */, X86::VMOVDDUPrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15009   { 11567 /* vmovddup */, X86::VMOVDDUPYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15010   { 11567 /* vmovddup */, X86::VMOVDDUPZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15011   { 11567 /* vmovddup */, X86::VMOVDDUPZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15012   { 11567 /* vmovddup */, X86::VMOVDDUPZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15030   { 11576 /* vmovdqa */, X86::VMOVDQArr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15032   { 11576 /* vmovdqa */, X86::VMOVDQAYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15036   { 11584 /* vmovdqa.s */, X86::VMOVDQArr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15037   { 11584 /* vmovdqa.s */, X86::VMOVDQAYrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15038   { 11594 /* vmovdqa32 */, X86::VMOVDQA32Z128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15040   { 11594 /* vmovdqa32 */, X86::VMOVDQA32Z256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15042   { 11594 /* vmovdqa32 */, X86::VMOVDQA32Zrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15062   { 11604 /* vmovdqa32.s */, X86::VMOVDQA32Z128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15063   { 11604 /* vmovdqa32.s */, X86::VMOVDQA32Z256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15064   { 11604 /* vmovdqa32.s */, X86::VMOVDQA32Zrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15071   { 11616 /* vmovdqa64 */, X86::VMOVDQA64Z128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15073   { 11616 /* vmovdqa64 */, X86::VMOVDQA64Z256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15075   { 11616 /* vmovdqa64 */, X86::VMOVDQA64Zrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15095   { 11626 /* vmovdqa64.s */, X86::VMOVDQA64Z128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15096   { 11626 /* vmovdqa64.s */, X86::VMOVDQA64Z256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15097   { 11626 /* vmovdqa64.s */, X86::VMOVDQA64Zrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15104   { 11638 /* vmovdqu */, X86::VMOVDQUrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15106   { 11638 /* vmovdqu */, X86::VMOVDQUYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15110   { 11646 /* vmovdqu.s */, X86::VMOVDQUrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15111   { 11646 /* vmovdqu.s */, X86::VMOVDQUYrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15112   { 11656 /* vmovdqu16 */, X86::VMOVDQU16Z128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15114   { 11656 /* vmovdqu16 */, X86::VMOVDQU16Z256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15116   { 11656 /* vmovdqu16 */, X86::VMOVDQU16Zrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15136   { 11666 /* vmovdqu16.s */, X86::VMOVDQU16Z128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15137   { 11666 /* vmovdqu16.s */, X86::VMOVDQU16Z256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15138   { 11666 /* vmovdqu16.s */, X86::VMOVDQU16Zrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15145   { 11678 /* vmovdqu32 */, X86::VMOVDQU32Z128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15147   { 11678 /* vmovdqu32 */, X86::VMOVDQU32Z256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15149   { 11678 /* vmovdqu32 */, X86::VMOVDQU32Zrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15169   { 11688 /* vmovdqu32.s */, X86::VMOVDQU32Z128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15170   { 11688 /* vmovdqu32.s */, X86::VMOVDQU32Z256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15171   { 11688 /* vmovdqu32.s */, X86::VMOVDQU32Zrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15178   { 11700 /* vmovdqu64 */, X86::VMOVDQU64Z128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15180   { 11700 /* vmovdqu64 */, X86::VMOVDQU64Z256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15182   { 11700 /* vmovdqu64 */, X86::VMOVDQU64Zrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15202   { 11710 /* vmovdqu64.s */, X86::VMOVDQU64Z128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15203   { 11710 /* vmovdqu64.s */, X86::VMOVDQU64Z256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15204   { 11710 /* vmovdqu64.s */, X86::VMOVDQU64Zrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15211   { 11722 /* vmovdqu8 */, X86::VMOVDQU8Z128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15213   { 11722 /* vmovdqu8 */, X86::VMOVDQU8Z256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15215   { 11722 /* vmovdqu8 */, X86::VMOVDQU8Zrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15235   { 11731 /* vmovdqu8.s */, X86::VMOVDQU8Z128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15236   { 11731 /* vmovdqu8.s */, X86::VMOVDQU8Z256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15237   { 11731 /* vmovdqu8.s */, X86::VMOVDQU8Zrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15288   { 11849 /* vmovq */, X86::VMOVZPQILo2PQIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15289   { 11849 /* vmovq */, X86::VMOVPQIto64rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_GR64 }, },
15291   { 11849 /* vmovq */, X86::VMOV64toPQIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32 }, },
15292   { 11849 /* vmovq */, X86::VMOV64toPQIZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X }, },
15293   { 11849 /* vmovq */, X86::VMOVPQIto64Zrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_GR64 }, },
15294   { 11849 /* vmovq */, X86::VMOVZPQILo2PQIZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15298   { 11855 /* vmovq.s */, X86::VMOVPQI2QIrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15299   { 11855 /* vmovq.s */, X86::VMOVPQI2QIZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15315   { 11879 /* vmovshdup */, X86::VMOVSHDUPrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15316   { 11879 /* vmovshdup */, X86::VMOVSHDUPYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15317   { 11879 /* vmovshdup */, X86::VMOVSHDUPZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15318   { 11879 /* vmovshdup */, X86::VMOVSHDUPZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15319   { 11879 /* vmovshdup */, X86::VMOVSHDUPZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15337   { 11889 /* vmovsldup */, X86::VMOVSLDUPrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15338   { 11889 /* vmovsldup */, X86::VMOVSLDUPYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15339   { 11889 /* vmovsldup */, X86::VMOVSLDUPZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15340   { 11889 /* vmovsldup */, X86::VMOVSLDUPZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15341   { 11889 /* vmovsldup */, X86::VMOVSLDUPZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15374   { 11915 /* vmovupd */, X86::VMOVUPDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15376   { 11915 /* vmovupd */, X86::VMOVUPDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15378   { 11915 /* vmovupd */, X86::VMOVUPDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15380   { 11915 /* vmovupd */, X86::VMOVUPDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15382   { 11915 /* vmovupd */, X86::VMOVUPDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15404   { 11923 /* vmovupd.s */, X86::VMOVUPDrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15405   { 11923 /* vmovupd.s */, X86::VMOVUPDYrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15406   { 11923 /* vmovupd.s */, X86::VMOVUPDZ128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15407   { 11923 /* vmovupd.s */, X86::VMOVUPDZ256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15408   { 11923 /* vmovupd.s */, X86::VMOVUPDZrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15415   { 11933 /* vmovups */, X86::VMOVUPSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15417   { 11933 /* vmovups */, X86::VMOVUPSYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15419   { 11933 /* vmovups */, X86::VMOVUPSZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15421   { 11933 /* vmovups */, X86::VMOVUPSZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15423   { 11933 /* vmovups */, X86::VMOVUPSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15445   { 11941 /* vmovups.s */, X86::VMOVUPSrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15446   { 11941 /* vmovups.s */, X86::VMOVUPSYrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15447   { 11941 /* vmovups.s */, X86::VMOVUPSZ128rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15448   { 11941 /* vmovups.s */, X86::VMOVUPSZ256rr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15449   { 11941 /* vmovups.s */, X86::VMOVUPSZrr_REV, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15462   { 11983 /* vmreadl */, X86::VMREAD32rr, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_GR32, MCK_GR32 }, },
15464   { 11991 /* vmreadq */, X86::VMREAD64rr, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_GR64, MCK_GR64 }, },
15561   { 12057 /* vmwritel */, X86::VMWRITE32rr, Convert__Reg1_1__Reg1_0, AMFBS_Not64BitMode, { MCK_GR32, MCK_GR32 }, },
15563   { 12066 /* vmwriteq */, X86::VMWRITE64rr, Convert__Reg1_1__Reg1_0, AMFBS_In64BitMode, { MCK_GR64, MCK_GR64 }, },
15653   { 12149 /* vpabsb */, X86::VPABSBrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15654   { 12149 /* vpabsb */, X86::VPABSBYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15655   { 12149 /* vpabsb */, X86::VPABSBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15656   { 12149 /* vpabsb */, X86::VPABSBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15657   { 12149 /* vpabsb */, X86::VPABSBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15675   { 12156 /* vpabsd */, X86::VPABSDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15676   { 12156 /* vpabsd */, X86::VPABSDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15677   { 12156 /* vpabsd */, X86::VPABSDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15678   { 12156 /* vpabsd */, X86::VPABSDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15679   { 12156 /* vpabsd */, X86::VPABSDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15706   { 12163 /* vpabsq */, X86::VPABSQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15707   { 12163 /* vpabsq */, X86::VPABSQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15708   { 12163 /* vpabsq */, X86::VPABSQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
15733   { 12170 /* vpabsw */, X86::VPABSWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
15734   { 12170 /* vpabsw */, X86::VPABSWYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
15735   { 12170 /* vpabsw */, X86::VPABSWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
15736   { 12170 /* vpabsw */, X86::VPABSWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
15737   { 12170 /* vpabsw */, X86::VPABSWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
16339   { 12413 /* vpbroadcastb */, X86::VPBROADCASTBrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
16340   { 12413 /* vpbroadcastb */, X86::VPBROADCASTBYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
16341   { 12413 /* vpbroadcastb */, X86::VPBROADCASTBrZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X }, },
16342   { 12413 /* vpbroadcastb */, X86::VPBROADCASTBrZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VR256X }, },
16343   { 12413 /* vpbroadcastb */, X86::VPBROADCASTBrZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VR512 }, },
16344   { 12413 /* vpbroadcastb */, X86::VPBROADCASTBZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16345   { 12413 /* vpbroadcastb */, X86::VPBROADCASTBZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
16346   { 12413 /* vpbroadcastb */, X86::VPBROADCASTBZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
16370   { 12426 /* vpbroadcastd */, X86::VPBROADCASTDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
16371   { 12426 /* vpbroadcastd */, X86::VPBROADCASTDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
16372   { 12426 /* vpbroadcastd */, X86::VPBROADCASTDrZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X }, },
16373   { 12426 /* vpbroadcastd */, X86::VPBROADCASTDrZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VR256X }, },
16374   { 12426 /* vpbroadcastd */, X86::VPBROADCASTDrZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VR512 }, },
16375   { 12426 /* vpbroadcastd */, X86::VPBROADCASTDZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16376   { 12426 /* vpbroadcastd */, X86::VPBROADCASTDZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
16377   { 12426 /* vpbroadcastd */, X86::VPBROADCASTDZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
16401   { 12439 /* vpbroadcastmb2q */, X86::VPBROADCASTMB2QZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_FR32X }, },
16402   { 12439 /* vpbroadcastmb2q */, X86::VPBROADCASTMB2QZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR256X }, },
16403   { 12439 /* vpbroadcastmb2q */, X86::VPBROADCASTMB2QZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR512 }, },
16404   { 12455 /* vpbroadcastmw2d */, X86::VPBROADCASTMW2DZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_FR32X }, },
16405   { 12455 /* vpbroadcastmw2d */, X86::VPBROADCASTMW2DZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR256X }, },
16406   { 12455 /* vpbroadcastmw2d */, X86::VPBROADCASTMW2DZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR512 }, },
16407   { 12471 /* vpbroadcastq */, X86::VPBROADCASTQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
16408   { 12471 /* vpbroadcastq */, X86::VPBROADCASTQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
16409   { 12471 /* vpbroadcastq */, X86::VPBROADCASTQrZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_FR32X }, },
16410   { 12471 /* vpbroadcastq */, X86::VPBROADCASTQrZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_VR256X }, },
16411   { 12471 /* vpbroadcastq */, X86::VPBROADCASTQrZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR64, MCK_VR512 }, },
16412   { 12471 /* vpbroadcastq */, X86::VPBROADCASTQZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16413   { 12471 /* vpbroadcastq */, X86::VPBROADCASTQZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
16414   { 12471 /* vpbroadcastq */, X86::VPBROADCASTQZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
16438   { 12484 /* vpbroadcastw */, X86::VPBROADCASTWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
16439   { 12484 /* vpbroadcastw */, X86::VPBROADCASTWYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
16440   { 12484 /* vpbroadcastw */, X86::VPBROADCASTWrZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_FR32X }, },
16441   { 12484 /* vpbroadcastw */, X86::VPBROADCASTWrZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VR256X }, },
16442   { 12484 /* vpbroadcastw */, X86::VPBROADCASTWrZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_VR512 }, },
16443   { 12484 /* vpbroadcastw */, X86::VPBROADCASTWZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16444   { 12484 /* vpbroadcastw */, X86::VPBROADCASTWZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
16445   { 12484 /* vpbroadcastw */, X86::VPBROADCASTWZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
16809   { 12761 /* vpcompressb */, X86::VPCOMPRESSBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16811   { 12761 /* vpcompressb */, X86::VPCOMPRESSBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
16813   { 12761 /* vpcompressb */, X86::VPCOMPRESSBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
16824   { 12773 /* vpcompressd */, X86::VPCOMPRESSDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16826   { 12773 /* vpcompressd */, X86::VPCOMPRESSDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
16828   { 12773 /* vpcompressd */, X86::VPCOMPRESSDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
16839   { 12785 /* vpcompressq */, X86::VPCOMPRESSQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16841   { 12785 /* vpcompressq */, X86::VPCOMPRESSQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
16843   { 12785 /* vpcompressq */, X86::VPCOMPRESSQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
16854   { 12797 /* vpcompressw */, X86::VPCOMPRESSWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16856   { 12797 /* vpcompressw */, X86::VPCOMPRESSWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
16858   { 12797 /* vpcompressw */, X86::VPCOMPRESSWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
16881   { 12855 /* vpconflictd */, X86::VPCONFLICTDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16882   { 12855 /* vpconflictd */, X86::VPCONFLICTDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
16883   { 12855 /* vpconflictd */, X86::VPCONFLICTDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
16908   { 12867 /* vpconflictq */, X86::VPCONFLICTQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
16909   { 12867 /* vpconflictq */, X86::VPCONFLICTQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
16910   { 12867 /* vpconflictq */, X86::VPCONFLICTQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
17623   { 13137 /* vpexpandb */, X86::VPEXPANDBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
17624   { 13137 /* vpexpandb */, X86::VPEXPANDBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
17625   { 13137 /* vpexpandb */, X86::VPEXPANDBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
17641   { 13147 /* vpexpandd */, X86::VPEXPANDDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
17642   { 13147 /* vpexpandd */, X86::VPEXPANDDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
17643   { 13147 /* vpexpandd */, X86::VPEXPANDDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
17659   { 13157 /* vpexpandq */, X86::VPEXPANDQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
17660   { 13157 /* vpexpandq */, X86::VPEXPANDQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
17661   { 13157 /* vpexpandq */, X86::VPEXPANDQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
17677   { 13167 /* vpexpandw */, X86::VPEXPANDWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
17678   { 13167 /* vpexpandw */, X86::VPEXPANDWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
17679   { 13167 /* vpexpandw */, X86::VPEXPANDWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
17731   { 13253 /* vphaddbd */, X86::VPHADDBDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17733   { 13262 /* vphaddbq */, X86::VPHADDBQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17735   { 13271 /* vphaddbw */, X86::VPHADDBWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17741   { 13288 /* vphadddq */, X86::VPHADDDQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17747   { 13306 /* vphaddubd */, X86::VPHADDUBDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17749   { 13316 /* vphaddubq */, X86::VPHADDUBQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17751   { 13326 /* vphaddubw */, X86::VPHADDUBWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17753   { 13336 /* vphaddudq */, X86::VPHADDUDQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17755   { 13346 /* vphadduwd */, X86::VPHADDUWDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17757   { 13356 /* vphadduwq */, X86::VPHADDUWQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17763   { 13374 /* vphaddwd */, X86::VPHADDWDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17765   { 13383 /* vphaddwq */, X86::VPHADDWQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17767   { 13392 /* vphminposuw */, X86::VPHMINPOSUWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17769   { 13404 /* vphsubbw */, X86::VPHSUBBWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17775   { 13421 /* vphsubdq */, X86::VPHSUBDQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17785   { 13447 /* vphsubwd */, X86::VPHSUBWDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
17803   { 13488 /* vplzcntd */, X86::VPLZCNTDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
17804   { 13488 /* vplzcntd */, X86::VPLZCNTDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
17805   { 13488 /* vplzcntd */, X86::VPLZCNTDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
17830   { 13497 /* vplzcntq */, X86::VPLZCNTQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
17831   { 13497 /* vplzcntq */, X86::VPLZCNTQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
17832   { 13497 /* vplzcntq */, X86::VPLZCNTQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
18395   { 13820 /* vpmovb2m */, X86::VPMOVB2MZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VK1 }, },
18396   { 13820 /* vpmovb2m */, X86::VPMOVB2MZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VK1 }, },
18397   { 13820 /* vpmovb2m */, X86::VPMOVB2MZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VK1 }, },
18398   { 13829 /* vpmovd2m */, X86::VPMOVD2MZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VK1 }, },
18399   { 13829 /* vpmovd2m */, X86::VPMOVD2MZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VK1 }, },
18400   { 13829 /* vpmovd2m */, X86::VPMOVD2MZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VK1 }, },
18401   { 13838 /* vpmovdb */, X86::VPMOVDBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18403   { 13838 /* vpmovdb */, X86::VPMOVDBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18405   { 13838 /* vpmovdb */, X86::VPMOVDBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_FR32X }, },
18416   { 13846 /* vpmovdw */, X86::VPMOVDWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18418   { 13846 /* vpmovdw */, X86::VPMOVDWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18420   { 13846 /* vpmovdw */, X86::VPMOVDWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
18431   { 13854 /* vpmovm2b */, X86::VPMOVM2BZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_FR32X }, },
18432   { 13854 /* vpmovm2b */, X86::VPMOVM2BZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR256X }, },
18433   { 13854 /* vpmovm2b */, X86::VPMOVM2BZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR512 }, },
18434   { 13863 /* vpmovm2d */, X86::VPMOVM2DZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_FR32X }, },
18435   { 13863 /* vpmovm2d */, X86::VPMOVM2DZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR256X }, },
18436   { 13863 /* vpmovm2d */, X86::VPMOVM2DZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR512 }, },
18437   { 13872 /* vpmovm2q */, X86::VPMOVM2QZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_FR32X }, },
18438   { 13872 /* vpmovm2q */, X86::VPMOVM2QZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR256X }, },
18439   { 13872 /* vpmovm2q */, X86::VPMOVM2QZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR512 }, },
18440   { 13881 /* vpmovm2w */, X86::VPMOVM2WZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_FR32X }, },
18441   { 13881 /* vpmovm2w */, X86::VPMOVM2WZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR256X }, },
18442   { 13881 /* vpmovm2w */, X86::VPMOVM2WZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VK1, MCK_VR512 }, },
18445   { 13900 /* vpmovq2m */, X86::VPMOVQ2MZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VK1 }, },
18446   { 13900 /* vpmovq2m */, X86::VPMOVQ2MZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VK1 }, },
18447   { 13900 /* vpmovq2m */, X86::VPMOVQ2MZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VK1 }, },
18448   { 13909 /* vpmovqb */, X86::VPMOVQBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18450   { 13909 /* vpmovqb */, X86::VPMOVQBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18452   { 13909 /* vpmovqb */, X86::VPMOVQBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_FR32X }, },
18463   { 13917 /* vpmovqd */, X86::VPMOVQDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18465   { 13917 /* vpmovqd */, X86::VPMOVQDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18467   { 13917 /* vpmovqd */, X86::VPMOVQDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
18478   { 13925 /* vpmovqw */, X86::VPMOVQWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18480   { 13925 /* vpmovqw */, X86::VPMOVQWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18482   { 13925 /* vpmovqw */, X86::VPMOVQWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_FR32X }, },
18493   { 13933 /* vpmovsdb */, X86::VPMOVSDBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18495   { 13933 /* vpmovsdb */, X86::VPMOVSDBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18497   { 13933 /* vpmovsdb */, X86::VPMOVSDBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_FR32X }, },
18508   { 13942 /* vpmovsdw */, X86::VPMOVSDWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18510   { 13942 /* vpmovsdw */, X86::VPMOVSDWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18512   { 13942 /* vpmovsdw */, X86::VPMOVSDWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
18523   { 13951 /* vpmovsqb */, X86::VPMOVSQBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18525   { 13951 /* vpmovsqb */, X86::VPMOVSQBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18527   { 13951 /* vpmovsqb */, X86::VPMOVSQBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_FR32X }, },
18538   { 13960 /* vpmovsqd */, X86::VPMOVSQDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18540   { 13960 /* vpmovsqd */, X86::VPMOVSQDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18542   { 13960 /* vpmovsqd */, X86::VPMOVSQDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
18553   { 13969 /* vpmovsqw */, X86::VPMOVSQWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18555   { 13969 /* vpmovsqw */, X86::VPMOVSQWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18557   { 13969 /* vpmovsqw */, X86::VPMOVSQWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_FR32X }, },
18568   { 13978 /* vpmovswb */, X86::VPMOVSWBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18570   { 13978 /* vpmovswb */, X86::VPMOVSWBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18572   { 13978 /* vpmovswb */, X86::VPMOVSWBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
18583   { 13987 /* vpmovsxbd */, X86::VPMOVSXBDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18584   { 13987 /* vpmovsxbd */, X86::VPMOVSXBDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18585   { 13987 /* vpmovsxbd */, X86::VPMOVSXBDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18586   { 13987 /* vpmovsxbd */, X86::VPMOVSXBDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18587   { 13987 /* vpmovsxbd */, X86::VPMOVSXBDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
18605   { 13997 /* vpmovsxbq */, X86::VPMOVSXBQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18606   { 13997 /* vpmovsxbq */, X86::VPMOVSXBQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18607   { 13997 /* vpmovsxbq */, X86::VPMOVSXBQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18608   { 13997 /* vpmovsxbq */, X86::VPMOVSXBQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18609   { 13997 /* vpmovsxbq */, X86::VPMOVSXBQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
18627   { 14007 /* vpmovsxbw */, X86::VPMOVSXBWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18628   { 14007 /* vpmovsxbw */, X86::VPMOVSXBWYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18629   { 14007 /* vpmovsxbw */, X86::VPMOVSXBWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18630   { 14007 /* vpmovsxbw */, X86::VPMOVSXBWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18631   { 14007 /* vpmovsxbw */, X86::VPMOVSXBWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
18649   { 14017 /* vpmovsxdq */, X86::VPMOVSXDQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18650   { 14017 /* vpmovsxdq */, X86::VPMOVSXDQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18651   { 14017 /* vpmovsxdq */, X86::VPMOVSXDQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18652   { 14017 /* vpmovsxdq */, X86::VPMOVSXDQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18653   { 14017 /* vpmovsxdq */, X86::VPMOVSXDQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
18671   { 14027 /* vpmovsxwd */, X86::VPMOVSXWDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18672   { 14027 /* vpmovsxwd */, X86::VPMOVSXWDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18673   { 14027 /* vpmovsxwd */, X86::VPMOVSXWDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18674   { 14027 /* vpmovsxwd */, X86::VPMOVSXWDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18675   { 14027 /* vpmovsxwd */, X86::VPMOVSXWDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
18693   { 14037 /* vpmovsxwq */, X86::VPMOVSXWQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18694   { 14037 /* vpmovsxwq */, X86::VPMOVSXWQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18695   { 14037 /* vpmovsxwq */, X86::VPMOVSXWQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18696   { 14037 /* vpmovsxwq */, X86::VPMOVSXWQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18697   { 14037 /* vpmovsxwq */, X86::VPMOVSXWQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
18715   { 14047 /* vpmovusdb */, X86::VPMOVUSDBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18717   { 14047 /* vpmovusdb */, X86::VPMOVUSDBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18719   { 14047 /* vpmovusdb */, X86::VPMOVUSDBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_FR32X }, },
18730   { 14057 /* vpmovusdw */, X86::VPMOVUSDWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18732   { 14057 /* vpmovusdw */, X86::VPMOVUSDWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18734   { 14057 /* vpmovusdw */, X86::VPMOVUSDWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
18745   { 14067 /* vpmovusqb */, X86::VPMOVUSQBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18747   { 14067 /* vpmovusqb */, X86::VPMOVUSQBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18749   { 14067 /* vpmovusqb */, X86::VPMOVUSQBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_FR32X }, },
18760   { 14077 /* vpmovusqd */, X86::VPMOVUSQDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18762   { 14077 /* vpmovusqd */, X86::VPMOVUSQDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18764   { 14077 /* vpmovusqd */, X86::VPMOVUSQDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
18775   { 14087 /* vpmovusqw */, X86::VPMOVUSQWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18777   { 14087 /* vpmovusqw */, X86::VPMOVUSQWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18779   { 14087 /* vpmovusqw */, X86::VPMOVUSQWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_FR32X }, },
18790   { 14097 /* vpmovuswb */, X86::VPMOVUSWBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18792   { 14097 /* vpmovuswb */, X86::VPMOVUSWBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18794   { 14097 /* vpmovuswb */, X86::VPMOVUSWBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
18805   { 14107 /* vpmovw2m */, X86::VPMOVW2MZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VK1 }, },
18806   { 14107 /* vpmovw2m */, X86::VPMOVW2MZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VK1 }, },
18807   { 14107 /* vpmovw2m */, X86::VPMOVW2MZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VK1 }, },
18808   { 14116 /* vpmovwb */, X86::VPMOVWBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18810   { 14116 /* vpmovwb */, X86::VPMOVWBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_FR32X }, },
18812   { 14116 /* vpmovwb */, X86::VPMOVWBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR256X }, },
18823   { 14124 /* vpmovzxbd */, X86::VPMOVZXBDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18824   { 14124 /* vpmovzxbd */, X86::VPMOVZXBDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18825   { 14124 /* vpmovzxbd */, X86::VPMOVZXBDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18826   { 14124 /* vpmovzxbd */, X86::VPMOVZXBDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18827   { 14124 /* vpmovzxbd */, X86::VPMOVZXBDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
18845   { 14134 /* vpmovzxbq */, X86::VPMOVZXBQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18846   { 14134 /* vpmovzxbq */, X86::VPMOVZXBQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18847   { 14134 /* vpmovzxbq */, X86::VPMOVZXBQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18848   { 14134 /* vpmovzxbq */, X86::VPMOVZXBQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18849   { 14134 /* vpmovzxbq */, X86::VPMOVZXBQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
18867   { 14144 /* vpmovzxbw */, X86::VPMOVZXBWrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18868   { 14144 /* vpmovzxbw */, X86::VPMOVZXBWYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18869   { 14144 /* vpmovzxbw */, X86::VPMOVZXBWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18870   { 14144 /* vpmovzxbw */, X86::VPMOVZXBWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18871   { 14144 /* vpmovzxbw */, X86::VPMOVZXBWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
18889   { 14154 /* vpmovzxdq */, X86::VPMOVZXDQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18890   { 14154 /* vpmovzxdq */, X86::VPMOVZXDQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18891   { 14154 /* vpmovzxdq */, X86::VPMOVZXDQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18892   { 14154 /* vpmovzxdq */, X86::VPMOVZXDQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18893   { 14154 /* vpmovzxdq */, X86::VPMOVZXDQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
18911   { 14164 /* vpmovzxwd */, X86::VPMOVZXWDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18912   { 14164 /* vpmovzxwd */, X86::VPMOVZXWDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18913   { 14164 /* vpmovzxwd */, X86::VPMOVZXWDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18914   { 14164 /* vpmovzxwd */, X86::VPMOVZXWDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18915   { 14164 /* vpmovzxwd */, X86::VPMOVZXWDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR512 }, },
18933   { 14174 /* vpmovzxwq */, X86::VPMOVZXWQrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
18934   { 14174 /* vpmovzxwq */, X86::VPMOVZXWQYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_VR256 }, },
18935   { 14174 /* vpmovzxwq */, X86::VPMOVZXWQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
18936   { 14174 /* vpmovzxwq */, X86::VPMOVZXWQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR256X }, },
18937   { 14174 /* vpmovzxwq */, X86::VPMOVZXWQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_VR512 }, },
19190   { 14267 /* vpopcntb */, X86::VPOPCNTBZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
19191   { 14267 /* vpopcntb */, X86::VPOPCNTBZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
19192   { 14267 /* vpopcntb */, X86::VPOPCNTBZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
19208   { 14276 /* vpopcntd */, X86::VPOPCNTDZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
19209   { 14276 /* vpopcntd */, X86::VPOPCNTDZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
19210   { 14276 /* vpopcntd */, X86::VPOPCNTDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
19235   { 14285 /* vpopcntq */, X86::VPOPCNTQZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
19236   { 14285 /* vpopcntq */, X86::VPOPCNTQZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
19237   { 14285 /* vpopcntq */, X86::VPOPCNTQZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
19262   { 14294 /* vpopcntw */, X86::VPOPCNTWZ128rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
19263   { 14294 /* vpopcntw */, X86::VPOPCNTWZ256rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
19264   { 14294 /* vpopcntw */, X86::VPOPCNTWZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
20958   { 14935 /* vptest */, X86::VPTESTrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
20959   { 14935 /* vptest */, X86::VPTESTYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
21430   { 15164 /* vrcp14pd */, X86::VRCP14PDZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
21431   { 15164 /* vrcp14pd */, X86::VRCP14PDZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
21432   { 15164 /* vrcp14pd */, X86::VRCP14PDZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
21457   { 15173 /* vrcp14ps */, X86::VRCP14PSZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
21458   { 15173 /* vrcp14ps */, X86::VRCP14PSZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
21459   { 15173 /* vrcp14ps */, X86::VRCP14PSZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
21496   { 15200 /* vrcp28pd */, X86::VRCP28PDZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
21508   { 15209 /* vrcp28ps */, X86::VRCP28PSZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
21538   { 15236 /* vrcpps */, X86::VRCPPSr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
21539   { 15236 /* vrcpps */, X86::VRCPPSYr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
21712   { 15374 /* vrsqrt14pd */, X86::VRSQRT14PDZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
21713   { 15374 /* vrsqrt14pd */, X86::VRSQRT14PDZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
21714   { 15374 /* vrsqrt14pd */, X86::VRSQRT14PDZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
21739   { 15385 /* vrsqrt14ps */, X86::VRSQRT14PSZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
21740   { 15385 /* vrsqrt14ps */, X86::VRSQRT14PSZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
21741   { 15385 /* vrsqrt14ps */, X86::VRSQRT14PSZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
21778   { 15418 /* vrsqrt28pd */, X86::VRSQRT28PDZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
21790   { 15429 /* vrsqrt28ps */, X86::VRSQRT28PSZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
21820   { 15462 /* vrsqrtps */, X86::VRSQRTPSr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
21821   { 15462 /* vrsqrtps */, X86::VRSQRTPSYr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
22058   { 15748 /* vsqrtpd */, X86::VSQRTPDr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
22059   { 15748 /* vsqrtpd */, X86::VSQRTPDYr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
22060   { 15748 /* vsqrtpd */, X86::VSQRTPDZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
22061   { 15748 /* vsqrtpd */, X86::VSQRTPDZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
22062   { 15748 /* vsqrtpd */, X86::VSQRTPDZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
22092   { 15756 /* vsqrtps */, X86::VSQRTPSr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
22093   { 15756 /* vsqrtps */, X86::VSQRTPSYr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
22094   { 15756 /* vsqrtps */, X86::VSQRTPSZ128r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
22095   { 15756 /* vsqrtps */, X86::VSQRTPSZ256r, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256X, MCK_VR256X }, },
22096   { 15756 /* vsqrtps */, X86::VSQRTPSZr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR512, MCK_VR512 }, },
22239   { 15817 /* vtestpd */, X86::VTESTPDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
22240   { 15817 /* vtestpd */, X86::VTESTPDYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
22243   { 15825 /* vtestps */, X86::VTESTPSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
22244   { 15825 /* vtestps */, X86::VTESTPSYrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_VR256, MCK_VR256 }, },
22247   { 15833 /* vucomisd */, X86::VUCOMISDrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
22248   { 15833 /* vucomisd */, X86::VUCOMISDZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },
22252   { 15842 /* vucomiss */, X86::VUCOMISSrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32, MCK_FR32 }, },
22253   { 15842 /* vucomiss */, X86::VUCOMISSZrr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_FR32X, MCK_FR32X }, },