reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

25116   { 8030 /* vaddpd */, X86::VADDPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
25118   { 8030 /* vaddpd */, X86::VADDPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
25120   { 8030 /* vaddpd */, X86::VADDPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
25150   { 8037 /* vaddps */, X86::VADDPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
25152   { 8037 /* vaddps */, X86::VADDPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
25154   { 8037 /* vaddps */, X86::VADDPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
25175   { 8044 /* vaddsd */, X86::VADDSDZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
25186   { 8051 /* vaddss */, X86::VADDSSZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
25311   { 8159 /* vandnpd */, X86::VANDNPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
25313   { 8159 /* vandnpd */, X86::VANDNPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
25315   { 8159 /* vandnpd */, X86::VANDNPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
25342   { 8167 /* vandnps */, X86::VANDNPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
25344   { 8167 /* vandnps */, X86::VANDNPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
25346   { 8167 /* vandnps */, X86::VANDNPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
25373   { 8175 /* vandpd */, X86::VANDPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
25375   { 8175 /* vandpd */, X86::VANDPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
25377   { 8175 /* vandpd */, X86::VANDPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
25404   { 8182 /* vandps */, X86::VANDPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
25406   { 8182 /* vandps */, X86::VANDPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
25408   { 8182 /* vandps */, X86::VANDPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
25774   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Z128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
25776   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Z256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
25778   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Zrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
26261   { 8876 /* vcvtsd2ss */, X86::VCVTSD2SSZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
26297   { 8985 /* vcvtss2sd */, X86::VCVTSS2SDZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
26301   { 8985 /* vcvtss2sd */, X86::VCVTSS2SDZrrb_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
26759   { 9498 /* vdivpd */, X86::VDIVPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
26761   { 9498 /* vdivpd */, X86::VDIVPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
26763   { 9498 /* vdivpd */, X86::VDIVPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
26793   { 9505 /* vdivps */, X86::VDIVPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
26795   { 9505 /* vdivps */, X86::VDIVPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
26797   { 9505 /* vdivps */, X86::VDIVPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
26818   { 9512 /* vdivsd */, X86::VDIVSDZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
26829   { 9519 /* vdivss */, X86::VDIVSSZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
26844   { 9526 /* vdpbf16ps */, X86::VDPBF16PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
26846   { 9526 /* vdpbf16ps */, X86::VDPBF16PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
26848   { 9526 /* vdpbf16ps */, X86::VDPBF16PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27092   { 9791 /* vfmadd132pd */, X86::VFMADD132PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27094   { 9791 /* vfmadd132pd */, X86::VFMADD132PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27096   { 9791 /* vfmadd132pd */, X86::VFMADD132PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27126   { 9803 /* vfmadd132ps */, X86::VFMADD132PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27128   { 9803 /* vfmadd132ps */, X86::VFMADD132PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27130   { 9803 /* vfmadd132ps */, X86::VFMADD132PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27151   { 9815 /* vfmadd132sd */, X86::VFMADD132SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27162   { 9827 /* vfmadd132ss */, X86::VFMADD132SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27182   { 9839 /* vfmadd213pd */, X86::VFMADD213PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27184   { 9839 /* vfmadd213pd */, X86::VFMADD213PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27186   { 9839 /* vfmadd213pd */, X86::VFMADD213PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27216   { 9851 /* vfmadd213ps */, X86::VFMADD213PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27218   { 9851 /* vfmadd213ps */, X86::VFMADD213PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27220   { 9851 /* vfmadd213ps */, X86::VFMADD213PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27241   { 9863 /* vfmadd213sd */, X86::VFMADD213SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27252   { 9875 /* vfmadd213ss */, X86::VFMADD213SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27272   { 9887 /* vfmadd231pd */, X86::VFMADD231PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27274   { 9887 /* vfmadd231pd */, X86::VFMADD231PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27276   { 9887 /* vfmadd231pd */, X86::VFMADD231PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27306   { 9899 /* vfmadd231ps */, X86::VFMADD231PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27308   { 9899 /* vfmadd231ps */, X86::VFMADD231PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27310   { 9899 /* vfmadd231ps */, X86::VFMADD231PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27331   { 9911 /* vfmadd231sd */, X86::VFMADD231SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27342   { 9923 /* vfmadd231ss */, X86::VFMADD231SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27380   { 9971 /* vfmaddsub132pd */, X86::VFMADDSUB132PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27382   { 9971 /* vfmaddsub132pd */, X86::VFMADDSUB132PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27384   { 9971 /* vfmaddsub132pd */, X86::VFMADDSUB132PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27414   { 9986 /* vfmaddsub132ps */, X86::VFMADDSUB132PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27416   { 9986 /* vfmaddsub132ps */, X86::VFMADDSUB132PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27418   { 9986 /* vfmaddsub132ps */, X86::VFMADDSUB132PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27448   { 10001 /* vfmaddsub213pd */, X86::VFMADDSUB213PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27450   { 10001 /* vfmaddsub213pd */, X86::VFMADDSUB213PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27452   { 10001 /* vfmaddsub213pd */, X86::VFMADDSUB213PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27482   { 10016 /* vfmaddsub213ps */, X86::VFMADDSUB213PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27484   { 10016 /* vfmaddsub213ps */, X86::VFMADDSUB213PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27486   { 10016 /* vfmaddsub213ps */, X86::VFMADDSUB213PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27516   { 10031 /* vfmaddsub231pd */, X86::VFMADDSUB231PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27518   { 10031 /* vfmaddsub231pd */, X86::VFMADDSUB231PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27520   { 10031 /* vfmaddsub231pd */, X86::VFMADDSUB231PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27550   { 10046 /* vfmaddsub231ps */, X86::VFMADDSUB231PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27552   { 10046 /* vfmaddsub231ps */, X86::VFMADDSUB231PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27554   { 10046 /* vfmaddsub231ps */, X86::VFMADDSUB231PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27596   { 10085 /* vfmsub132pd */, X86::VFMSUB132PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27598   { 10085 /* vfmsub132pd */, X86::VFMSUB132PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27600   { 10085 /* vfmsub132pd */, X86::VFMSUB132PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27630   { 10097 /* vfmsub132ps */, X86::VFMSUB132PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27632   { 10097 /* vfmsub132ps */, X86::VFMSUB132PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27634   { 10097 /* vfmsub132ps */, X86::VFMSUB132PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27655   { 10109 /* vfmsub132sd */, X86::VFMSUB132SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27666   { 10121 /* vfmsub132ss */, X86::VFMSUB132SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27686   { 10133 /* vfmsub213pd */, X86::VFMSUB213PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27688   { 10133 /* vfmsub213pd */, X86::VFMSUB213PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27690   { 10133 /* vfmsub213pd */, X86::VFMSUB213PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27720   { 10145 /* vfmsub213ps */, X86::VFMSUB213PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27722   { 10145 /* vfmsub213ps */, X86::VFMSUB213PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27724   { 10145 /* vfmsub213ps */, X86::VFMSUB213PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27745   { 10157 /* vfmsub213sd */, X86::VFMSUB213SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27756   { 10169 /* vfmsub213ss */, X86::VFMSUB213SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27776   { 10181 /* vfmsub231pd */, X86::VFMSUB231PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27778   { 10181 /* vfmsub231pd */, X86::VFMSUB231PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27780   { 10181 /* vfmsub231pd */, X86::VFMSUB231PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27810   { 10193 /* vfmsub231ps */, X86::VFMSUB231PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27812   { 10193 /* vfmsub231ps */, X86::VFMSUB231PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27814   { 10193 /* vfmsub231ps */, X86::VFMSUB231PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27835   { 10205 /* vfmsub231sd */, X86::VFMSUB231SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27846   { 10217 /* vfmsub231ss */, X86::VFMSUB231SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27866   { 10229 /* vfmsubadd132pd */, X86::VFMSUBADD132PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27868   { 10229 /* vfmsubadd132pd */, X86::VFMSUBADD132PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27870   { 10229 /* vfmsubadd132pd */, X86::VFMSUBADD132PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27900   { 10244 /* vfmsubadd132ps */, X86::VFMSUBADD132PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27902   { 10244 /* vfmsubadd132ps */, X86::VFMSUBADD132PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27904   { 10244 /* vfmsubadd132ps */, X86::VFMSUBADD132PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27934   { 10259 /* vfmsubadd213pd */, X86::VFMSUBADD213PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27936   { 10259 /* vfmsubadd213pd */, X86::VFMSUBADD213PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27938   { 10259 /* vfmsubadd213pd */, X86::VFMSUBADD213PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
27968   { 10274 /* vfmsubadd213ps */, X86::VFMSUBADD213PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
27970   { 10274 /* vfmsubadd213ps */, X86::VFMSUBADD213PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
27972   { 10274 /* vfmsubadd213ps */, X86::VFMSUBADD213PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28002   { 10289 /* vfmsubadd231pd */, X86::VFMSUBADD231PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28004   { 10289 /* vfmsubadd231pd */, X86::VFMSUBADD231PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28006   { 10289 /* vfmsubadd231pd */, X86::VFMSUBADD231PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28036   { 10304 /* vfmsubadd231ps */, X86::VFMSUBADD231PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28038   { 10304 /* vfmsubadd231ps */, X86::VFMSUBADD231PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28040   { 10304 /* vfmsubadd231ps */, X86::VFMSUBADD231PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28100   { 10379 /* vfnmadd132pd */, X86::VFNMADD132PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28102   { 10379 /* vfnmadd132pd */, X86::VFNMADD132PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28104   { 10379 /* vfnmadd132pd */, X86::VFNMADD132PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28134   { 10392 /* vfnmadd132ps */, X86::VFNMADD132PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28136   { 10392 /* vfnmadd132ps */, X86::VFNMADD132PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28138   { 10392 /* vfnmadd132ps */, X86::VFNMADD132PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28159   { 10405 /* vfnmadd132sd */, X86::VFNMADD132SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28170   { 10418 /* vfnmadd132ss */, X86::VFNMADD132SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28190   { 10431 /* vfnmadd213pd */, X86::VFNMADD213PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28192   { 10431 /* vfnmadd213pd */, X86::VFNMADD213PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28194   { 10431 /* vfnmadd213pd */, X86::VFNMADD213PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28224   { 10444 /* vfnmadd213ps */, X86::VFNMADD213PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28226   { 10444 /* vfnmadd213ps */, X86::VFNMADD213PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28228   { 10444 /* vfnmadd213ps */, X86::VFNMADD213PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28249   { 10457 /* vfnmadd213sd */, X86::VFNMADD213SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28260   { 10470 /* vfnmadd213ss */, X86::VFNMADD213SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28280   { 10483 /* vfnmadd231pd */, X86::VFNMADD231PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28282   { 10483 /* vfnmadd231pd */, X86::VFNMADD231PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28284   { 10483 /* vfnmadd231pd */, X86::VFNMADD231PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28314   { 10496 /* vfnmadd231ps */, X86::VFNMADD231PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28316   { 10496 /* vfnmadd231ps */, X86::VFNMADD231PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28318   { 10496 /* vfnmadd231ps */, X86::VFNMADD231PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28339   { 10509 /* vfnmadd231sd */, X86::VFNMADD231SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28350   { 10522 /* vfnmadd231ss */, X86::VFNMADD231SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28388   { 10575 /* vfnmsub132pd */, X86::VFNMSUB132PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28390   { 10575 /* vfnmsub132pd */, X86::VFNMSUB132PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28392   { 10575 /* vfnmsub132pd */, X86::VFNMSUB132PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28422   { 10588 /* vfnmsub132ps */, X86::VFNMSUB132PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28424   { 10588 /* vfnmsub132ps */, X86::VFNMSUB132PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28426   { 10588 /* vfnmsub132ps */, X86::VFNMSUB132PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28447   { 10601 /* vfnmsub132sd */, X86::VFNMSUB132SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28458   { 10614 /* vfnmsub132ss */, X86::VFNMSUB132SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28478   { 10627 /* vfnmsub213pd */, X86::VFNMSUB213PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28480   { 10627 /* vfnmsub213pd */, X86::VFNMSUB213PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28482   { 10627 /* vfnmsub213pd */, X86::VFNMSUB213PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28512   { 10640 /* vfnmsub213ps */, X86::VFNMSUB213PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28514   { 10640 /* vfnmsub213ps */, X86::VFNMSUB213PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28516   { 10640 /* vfnmsub213ps */, X86::VFNMSUB213PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28537   { 10653 /* vfnmsub213sd */, X86::VFNMSUB213SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28548   { 10666 /* vfnmsub213ss */, X86::VFNMSUB213SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28568   { 10679 /* vfnmsub231pd */, X86::VFNMSUB231PDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28570   { 10679 /* vfnmsub231pd */, X86::VFNMSUB231PDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28572   { 10679 /* vfnmsub231pd */, X86::VFNMSUB231PDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28602   { 10692 /* vfnmsub231ps */, X86::VFNMSUB231PSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28604   { 10692 /* vfnmsub231ps */, X86::VFNMSUB231PSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28606   { 10692 /* vfnmsub231ps */, X86::VFNMSUB231PSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
28627   { 10705 /* vfnmsub231sd */, X86::VFNMSUB231SDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28638   { 10718 /* vfnmsub231ss */, X86::VFNMSUB231SSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28809   { 11095 /* vgetexpsd */, X86::VGETEXPSDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28813   { 11095 /* vgetexpsd */, X86::VGETEXPSDZrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
28818   { 11105 /* vgetexpss */, X86::VGETEXPSSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28822   { 11105 /* vgetexpss */, X86::VGETEXPSSZrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
28974   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
28976   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
28978   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
29109   { 11423 /* vmaxpd */, X86::VMAXPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29111   { 11423 /* vmaxpd */, X86::VMAXPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
29113   { 11423 /* vmaxpd */, X86::VMAXPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
29123   { 11423 /* vmaxpd */, X86::VMAXPDZrrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29143   { 11430 /* vmaxps */, X86::VMAXPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29145   { 11430 /* vmaxps */, X86::VMAXPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
29147   { 11430 /* vmaxps */, X86::VMAXPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
29157   { 11430 /* vmaxps */, X86::VMAXPSZrrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29168   { 11437 /* vmaxsd */, X86::VMAXSDZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29172   { 11437 /* vmaxsd */, X86::VMAXSDZrrb_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29179   { 11444 /* vmaxss */, X86::VMAXSSZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29183   { 11444 /* vmaxss */, X86::VMAXSSZrrb_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29202   { 11473 /* vminpd */, X86::VMINPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29204   { 11473 /* vminpd */, X86::VMINPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
29206   { 11473 /* vminpd */, X86::VMINPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
29216   { 11473 /* vminpd */, X86::VMINPDZrrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29236   { 11480 /* vminps */, X86::VMINPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29238   { 11480 /* vminps */, X86::VMINPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
29240   { 11480 /* vminps */, X86::VMINPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
29250   { 11480 /* vminps */, X86::VMINPSZrrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29261   { 11487 /* vminsd */, X86::VMINSDZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29265   { 11487 /* vminsd */, X86::VMINSDZrrb_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29272   { 11494 /* vminss */, X86::VMINSSZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29276   { 11494 /* vminss */, X86::VMINSSZrrb_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29677   { 11863 /* vmovsd */, X86::VMOVSDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29681   { 11870 /* vmovsd.s */, X86::VMOVSDZrrk_REV, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29736   { 11899 /* vmovss */, X86::VMOVSSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29740   { 11906 /* vmovss.s */, X86::VMOVSSZrrk_REV, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29853   { 12021 /* vmulpd */, X86::VMULPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29855   { 12021 /* vmulpd */, X86::VMULPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
29857   { 12021 /* vmulpd */, X86::VMULPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
29887   { 12028 /* vmulps */, X86::VMULPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29889   { 12028 /* vmulps */, X86::VMULPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
29891   { 12028 /* vmulps */, X86::VMULPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
29912   { 12035 /* vmulsd */, X86::VMULSDZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29923   { 12042 /* vmulss */, X86::VMULSSZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29948   { 12088 /* vorpd */, X86::VORPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29950   { 12088 /* vorpd */, X86::VORPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
29952   { 12088 /* vorpd */, X86::VORPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
29979   { 12094 /* vorps */, X86::VORPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
29981   { 12094 /* vorps */, X86::VORPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
29983   { 12094 /* vorps */, X86::VORPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30136   { 12177 /* vpackssdw */, X86::VPACKSSDWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30138   { 12177 /* vpackssdw */, X86::VPACKSSDWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30140   { 12177 /* vpackssdw */, X86::VPACKSSDWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30164   { 12187 /* vpacksswb */, X86::VPACKSSWBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30166   { 12187 /* vpacksswb */, X86::VPACKSSWBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30168   { 12187 /* vpacksswb */, X86::VPACKSSWBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30189   { 12197 /* vpackusdw */, X86::VPACKUSDWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30191   { 12197 /* vpackusdw */, X86::VPACKUSDWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30193   { 12197 /* vpackusdw */, X86::VPACKUSDWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30217   { 12207 /* vpackuswb */, X86::VPACKUSWBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30219   { 12207 /* vpackuswb */, X86::VPACKUSWBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30221   { 12207 /* vpackuswb */, X86::VPACKUSWBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30239   { 12217 /* vpaddb */, X86::VPADDBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30241   { 12217 /* vpaddb */, X86::VPADDBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30243   { 12217 /* vpaddb */, X86::VPADDBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30264   { 12224 /* vpaddd */, X86::VPADDDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30266   { 12224 /* vpaddd */, X86::VPADDDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30268   { 12224 /* vpaddd */, X86::VPADDDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30295   { 12231 /* vpaddq */, X86::VPADDQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30297   { 12231 /* vpaddq */, X86::VPADDQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30299   { 12231 /* vpaddq */, X86::VPADDQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30323   { 12238 /* vpaddsb */, X86::VPADDSBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30325   { 12238 /* vpaddsb */, X86::VPADDSBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30327   { 12238 /* vpaddsb */, X86::VPADDSBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30345   { 12246 /* vpaddsw */, X86::VPADDSWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30347   { 12246 /* vpaddsw */, X86::VPADDSWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30349   { 12246 /* vpaddsw */, X86::VPADDSWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30367   { 12254 /* vpaddusb */, X86::VPADDUSBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30369   { 12254 /* vpaddusb */, X86::VPADDUSBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30371   { 12254 /* vpaddusb */, X86::VPADDUSBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30389   { 12263 /* vpaddusw */, X86::VPADDUSWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30391   { 12263 /* vpaddusw */, X86::VPADDUSWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30393   { 12263 /* vpaddusw */, X86::VPADDUSWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30411   { 12272 /* vpaddw */, X86::VPADDWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30413   { 12272 /* vpaddw */, X86::VPADDWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30415   { 12272 /* vpaddw */, X86::VPADDWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30458   { 12294 /* vpandd */, X86::VPANDDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30460   { 12294 /* vpandd */, X86::VPANDDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30462   { 12294 /* vpandd */, X86::VPANDDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30489   { 12308 /* vpandnd */, X86::VPANDNDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30491   { 12308 /* vpandnd */, X86::VPANDNDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30493   { 12308 /* vpandnd */, X86::VPANDNDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30516   { 12316 /* vpandnq */, X86::VPANDNQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30518   { 12316 /* vpandnq */, X86::VPANDNQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30520   { 12316 /* vpandnq */, X86::VPANDNQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30543   { 12324 /* vpandq */, X86::VPANDQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30545   { 12324 /* vpandq */, X86::VPANDQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30547   { 12324 /* vpandq */, X86::VPANDQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30571   { 12331 /* vpavgb */, X86::VPAVGBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30573   { 12331 /* vpavgb */, X86::VPAVGBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30575   { 12331 /* vpavgb */, X86::VPAVGBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
30593   { 12338 /* vpavgw */, X86::VPAVGWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
30595   { 12338 /* vpavgw */, X86::VPAVGWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
30597   { 12338 /* vpavgw */, X86::VPAVGWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31312   { 12879 /* vpdpbusd */, X86::VPDPBUSDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31314   { 12879 /* vpdpbusd */, X86::VPDPBUSDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31316   { 12879 /* vpdpbusd */, X86::VPDPBUSDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31339   { 12888 /* vpdpbusds */, X86::VPDPBUSDSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31341   { 12888 /* vpdpbusds */, X86::VPDPBUSDSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31343   { 12888 /* vpdpbusds */, X86::VPDPBUSDSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31366   { 12898 /* vpdpwssd */, X86::VPDPWSSDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31368   { 12898 /* vpdpwssd */, X86::VPDPWSSDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31370   { 12898 /* vpdpwssd */, X86::VPDPWSSDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31393   { 12907 /* vpdpwssds */, X86::VPDPWSSDSZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31395   { 12907 /* vpdpwssds */, X86::VPDPWSSDSZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31397   { 12907 /* vpdpwssds */, X86::VPDPWSSDSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31421   { 12939 /* vpermb */, X86::VPERMBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31423   { 12939 /* vpermb */, X86::VPERMBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31425   { 12939 /* vpermb */, X86::VPERMBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31441   { 12946 /* vpermd */, X86::VPERMDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31443   { 12946 /* vpermd */, X86::VPERMDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31459   { 12953 /* vpermi2b */, X86::VPERMI2B128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31461   { 12953 /* vpermi2b */, X86::VPERMI2B256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31463   { 12953 /* vpermi2b */, X86::VPERMI2Brrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31480   { 12962 /* vpermi2d */, X86::VPERMI2D128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31482   { 12962 /* vpermi2d */, X86::VPERMI2D256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31484   { 12962 /* vpermi2d */, X86::VPERMI2Drrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31507   { 12971 /* vpermi2pd */, X86::VPERMI2PD128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31509   { 12971 /* vpermi2pd */, X86::VPERMI2PD256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31511   { 12971 /* vpermi2pd */, X86::VPERMI2PDrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31534   { 12981 /* vpermi2ps */, X86::VPERMI2PS128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31536   { 12981 /* vpermi2ps */, X86::VPERMI2PS256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31538   { 12981 /* vpermi2ps */, X86::VPERMI2PSrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31561   { 12991 /* vpermi2q */, X86::VPERMI2Q128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31563   { 12991 /* vpermi2q */, X86::VPERMI2Q256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31565   { 12991 /* vpermi2q */, X86::VPERMI2Qrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31585   { 13000 /* vpermi2w */, X86::VPERMI2W128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31587   { 13000 /* vpermi2w */, X86::VPERMI2W256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31589   { 13000 /* vpermi2w */, X86::VPERMI2Wrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31635   { 13031 /* vpermilpd */, X86::VPERMILPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31639   { 13031 /* vpermilpd */, X86::VPERMILPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31643   { 13031 /* vpermilpd */, X86::VPERMILPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31697   { 13041 /* vpermilps */, X86::VPERMILPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31701   { 13041 /* vpermilps */, X86::VPERMILPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31705   { 13041 /* vpermilps */, X86::VPERMILPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31747   { 13051 /* vpermpd */, X86::VPERMPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31751   { 13051 /* vpermpd */, X86::VPERMPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31779   { 13059 /* vpermps */, X86::VPERMPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31781   { 13059 /* vpermps */, X86::VPERMPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31805   { 13067 /* vpermq */, X86::VPERMQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31809   { 13067 /* vpermq */, X86::VPERMQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31835   { 13074 /* vpermt2b */, X86::VPERMT2B128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31837   { 13074 /* vpermt2b */, X86::VPERMT2B256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31839   { 13074 /* vpermt2b */, X86::VPERMT2Brrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31856   { 13083 /* vpermt2d */, X86::VPERMT2D128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31858   { 13083 /* vpermt2d */, X86::VPERMT2D256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31860   { 13083 /* vpermt2d */, X86::VPERMT2Drrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31883   { 13092 /* vpermt2pd */, X86::VPERMT2PD128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31885   { 13092 /* vpermt2pd */, X86::VPERMT2PD256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31887   { 13092 /* vpermt2pd */, X86::VPERMT2PDrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31910   { 13102 /* vpermt2ps */, X86::VPERMT2PS128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31912   { 13102 /* vpermt2ps */, X86::VPERMT2PS256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31914   { 13102 /* vpermt2ps */, X86::VPERMT2PSrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31937   { 13112 /* vpermt2q */, X86::VPERMT2Q128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31939   { 13112 /* vpermt2q */, X86::VPERMT2Q256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31941   { 13112 /* vpermt2q */, X86::VPERMT2Qrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31961   { 13121 /* vpermt2w */, X86::VPERMT2W128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31963   { 13121 /* vpermt2w */, X86::VPERMT2W256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31965   { 13121 /* vpermt2w */, X86::VPERMT2Wrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
31979   { 13130 /* vpermw */, X86::VPERMWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
31981   { 13130 /* vpermw */, X86::VPERMWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
31983   { 13130 /* vpermw */, X86::VPERMWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32258   { 13626 /* vpmadd52huq */, X86::VPMADD52HUQZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32260   { 13626 /* vpmadd52huq */, X86::VPMADD52HUQZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32262   { 13626 /* vpmadd52huq */, X86::VPMADD52HUQZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32285   { 13638 /* vpmadd52luq */, X86::VPMADD52LUQZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32287   { 13638 /* vpmadd52luq */, X86::VPMADD52LUQZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32289   { 13638 /* vpmadd52luq */, X86::VPMADD52LUQZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32313   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32315   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32317   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32335   { 13661 /* vpmaddwd */, X86::VPMADDWDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32337   { 13661 /* vpmaddwd */, X86::VPMADDWDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32339   { 13661 /* vpmaddwd */, X86::VPMADDWDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32365   { 13692 /* vpmaxsb */, X86::VPMAXSBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32367   { 13692 /* vpmaxsb */, X86::VPMAXSBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32369   { 13692 /* vpmaxsb */, X86::VPMAXSBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32390   { 13700 /* vpmaxsd */, X86::VPMAXSDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32392   { 13700 /* vpmaxsd */, X86::VPMAXSDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32394   { 13700 /* vpmaxsd */, X86::VPMAXSDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32417   { 13708 /* vpmaxsq */, X86::VPMAXSQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32419   { 13708 /* vpmaxsq */, X86::VPMAXSQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32421   { 13708 /* vpmaxsq */, X86::VPMAXSQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32445   { 13716 /* vpmaxsw */, X86::VPMAXSWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32447   { 13716 /* vpmaxsw */, X86::VPMAXSWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32449   { 13716 /* vpmaxsw */, X86::VPMAXSWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32467   { 13724 /* vpmaxub */, X86::VPMAXUBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32469   { 13724 /* vpmaxub */, X86::VPMAXUBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32471   { 13724 /* vpmaxub */, X86::VPMAXUBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32492   { 13732 /* vpmaxud */, X86::VPMAXUDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32494   { 13732 /* vpmaxud */, X86::VPMAXUDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32496   { 13732 /* vpmaxud */, X86::VPMAXUDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32519   { 13740 /* vpmaxuq */, X86::VPMAXUQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32521   { 13740 /* vpmaxuq */, X86::VPMAXUQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32523   { 13740 /* vpmaxuq */, X86::VPMAXUQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32547   { 13748 /* vpmaxuw */, X86::VPMAXUWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32549   { 13748 /* vpmaxuw */, X86::VPMAXUWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32551   { 13748 /* vpmaxuw */, X86::VPMAXUWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32569   { 13756 /* vpminsb */, X86::VPMINSBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32571   { 13756 /* vpminsb */, X86::VPMINSBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32573   { 13756 /* vpminsb */, X86::VPMINSBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32594   { 13764 /* vpminsd */, X86::VPMINSDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32596   { 13764 /* vpminsd */, X86::VPMINSDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32598   { 13764 /* vpminsd */, X86::VPMINSDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32621   { 13772 /* vpminsq */, X86::VPMINSQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32623   { 13772 /* vpminsq */, X86::VPMINSQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32625   { 13772 /* vpminsq */, X86::VPMINSQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32649   { 13780 /* vpminsw */, X86::VPMINSWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32651   { 13780 /* vpminsw */, X86::VPMINSWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32653   { 13780 /* vpminsw */, X86::VPMINSWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32671   { 13788 /* vpminub */, X86::VPMINUBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32673   { 13788 /* vpminub */, X86::VPMINUBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32675   { 13788 /* vpminub */, X86::VPMINUBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32696   { 13796 /* vpminud */, X86::VPMINUDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32698   { 13796 /* vpminud */, X86::VPMINUDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32700   { 13796 /* vpminud */, X86::VPMINUDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32723   { 13804 /* vpminuq */, X86::VPMINUQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32725   { 13804 /* vpminuq */, X86::VPMINUQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32727   { 13804 /* vpminuq */, X86::VPMINUQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
32751   { 13812 /* vpminuw */, X86::VPMINUWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
32753   { 13812 /* vpminuw */, X86::VPMINUWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
32755   { 13812 /* vpminuw */, X86::VPMINUWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33336   { 14184 /* vpmuldq */, X86::VPMULDQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33338   { 14184 /* vpmuldq */, X86::VPMULDQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33340   { 14184 /* vpmuldq */, X86::VPMULDQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33364   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33366   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33368   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33386   { 14202 /* vpmulhuw */, X86::VPMULHUWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33388   { 14202 /* vpmulhuw */, X86::VPMULHUWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33390   { 14202 /* vpmulhuw */, X86::VPMULHUWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33408   { 14211 /* vpmulhw */, X86::VPMULHWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33410   { 14211 /* vpmulhw */, X86::VPMULHWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33412   { 14211 /* vpmulhw */, X86::VPMULHWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33433   { 14219 /* vpmulld */, X86::VPMULLDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33435   { 14219 /* vpmulld */, X86::VPMULLDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33437   { 14219 /* vpmulld */, X86::VPMULLDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33460   { 14227 /* vpmullq */, X86::VPMULLQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33462   { 14227 /* vpmullq */, X86::VPMULLQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33464   { 14227 /* vpmullq */, X86::VPMULLQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33488   { 14235 /* vpmullw */, X86::VPMULLWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33490   { 14235 /* vpmullw */, X86::VPMULLWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33492   { 14235 /* vpmullw */, X86::VPMULLWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33509   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33511   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33513   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33540   { 14258 /* vpmuludq */, X86::VPMULUDQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33542   { 14258 /* vpmuludq */, X86::VPMULUDQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33544   { 14258 /* vpmuludq */, X86::VPMULUDQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33661   { 14308 /* vpord */, X86::VPORDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33663   { 14308 /* vpord */, X86::VPORDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33665   { 14308 /* vpord */, X86::VPORDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33688   { 14314 /* vporq */, X86::VPORQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33690   { 14314 /* vporq */, X86::VPORQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33692   { 14314 /* vporq */, X86::VPORQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33772   { 14341 /* vprolvd */, X86::VPROLVDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33774   { 14341 /* vprolvd */, X86::VPROLVDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33776   { 14341 /* vprolvd */, X86::VPROLVDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33799   { 14349 /* vprolvq */, X86::VPROLVQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33801   { 14349 /* vprolvq */, X86::VPROLVQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33803   { 14349 /* vprolvq */, X86::VPROLVQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33880   { 14371 /* vprorvd */, X86::VPRORVDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33882   { 14371 /* vprorvd */, X86::VPRORVDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33884   { 14371 /* vprorvd */, X86::VPRORVDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
33907   { 14379 /* vprorvq */, X86::VPRORVQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
33909   { 14379 /* vprorvq */, X86::VPRORVQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
33911   { 14379 /* vprorvq */, X86::VPRORVQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34048   { 14529 /* vpshldvd */, X86::VPSHLDVDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34050   { 14529 /* vpshldvd */, X86::VPSHLDVDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34052   { 14529 /* vpshldvd */, X86::VPSHLDVDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34075   { 14538 /* vpshldvq */, X86::VPSHLDVQZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34077   { 14538 /* vpshldvq */, X86::VPSHLDVQZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34079   { 14538 /* vpshldvq */, X86::VPSHLDVQZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34099   { 14547 /* vpshldvw */, X86::VPSHLDVWZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34101   { 14547 /* vpshldvw */, X86::VPSHLDVWZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34103   { 14547 /* vpshldvw */, X86::VPSHLDVWZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34198   { 14594 /* vpshrdvd */, X86::VPSHRDVDZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34200   { 14594 /* vpshrdvd */, X86::VPSHRDVDZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34202   { 14594 /* vpshrdvd */, X86::VPSHRDVDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34225   { 14603 /* vpshrdvq */, X86::VPSHRDVQZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34227   { 14603 /* vpshrdvq */, X86::VPSHRDVQZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34229   { 14603 /* vpshrdvq */, X86::VPSHRDVQZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34249   { 14612 /* vpshrdvw */, X86::VPSHRDVWZ128rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34251   { 14612 /* vpshrdvw */, X86::VPSHRDVWZ256rk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34253   { 14612 /* vpshrdvw */, X86::VPSHRDVWZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34289   { 14629 /* vpshufb */, X86::VPSHUFBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34291   { 14629 /* vpshufb */, X86::VPSHUFBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34293   { 14629 /* vpshufb */, X86::VPSHUFBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34421   { 14700 /* vpslld */, X86::VPSLLDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34425   { 14700 /* vpslld */, X86::VPSLLDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_FR32X }, },
34429   { 14700 /* vpslld */, X86::VPSLLDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_FR32X }, },
34480   { 14715 /* vpsllq */, X86::VPSLLQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34484   { 14715 /* vpsllq */, X86::VPSLLQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_FR32X }, },
34488   { 14715 /* vpsllq */, X86::VPSLLQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_FR32X }, },
34523   { 14722 /* vpsllvd */, X86::VPSLLVDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34525   { 14722 /* vpsllvd */, X86::VPSLLVDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34527   { 14722 /* vpsllvd */, X86::VPSLLVDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34554   { 14730 /* vpsllvq */, X86::VPSLLVQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34556   { 14730 /* vpsllvq */, X86::VPSLLVQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34558   { 14730 /* vpsllvq */, X86::VPSLLVQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34578   { 14738 /* vpsllvw */, X86::VPSLLVWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34580   { 14738 /* vpsllvw */, X86::VPSLLVWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34582   { 14738 /* vpsllvw */, X86::VPSLLVWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34608   { 14746 /* vpsllw */, X86::VPSLLWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34612   { 14746 /* vpsllw */, X86::VPSLLWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_FR32X }, },
34616   { 14746 /* vpsllw */, X86::VPSLLWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_FR32X }, },
34653   { 14753 /* vpsrad */, X86::VPSRADZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34657   { 14753 /* vpsrad */, X86::VPSRADZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_FR32X }, },
34661   { 14753 /* vpsrad */, X86::VPSRADZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_FR32X }, },
34698   { 14760 /* vpsraq */, X86::VPSRAQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34702   { 14760 /* vpsraq */, X86::VPSRAQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_FR32X }, },
34706   { 14760 /* vpsraq */, X86::VPSRAQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_FR32X }, },
34741   { 14767 /* vpsravd */, X86::VPSRAVDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34743   { 14767 /* vpsravd */, X86::VPSRAVDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34745   { 14767 /* vpsravd */, X86::VPSRAVDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34768   { 14775 /* vpsravq */, X86::VPSRAVQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34770   { 14775 /* vpsravq */, X86::VPSRAVQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34772   { 14775 /* vpsravq */, X86::VPSRAVQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34792   { 14783 /* vpsravw */, X86::VPSRAVWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34794   { 14783 /* vpsravw */, X86::VPSRAVWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34796   { 14783 /* vpsravw */, X86::VPSRAVWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
34822   { 14791 /* vpsraw */, X86::VPSRAWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34826   { 14791 /* vpsraw */, X86::VPSRAWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_FR32X }, },
34830   { 14791 /* vpsraw */, X86::VPSRAWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_FR32X }, },
34867   { 14798 /* vpsrld */, X86::VPSRLDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34871   { 14798 /* vpsrld */, X86::VPSRLDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_FR32X }, },
34875   { 14798 /* vpsrld */, X86::VPSRLDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_FR32X }, },
34926   { 14813 /* vpsrlq */, X86::VPSRLQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34930   { 14813 /* vpsrlq */, X86::VPSRLQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_FR32X }, },
34934   { 14813 /* vpsrlq */, X86::VPSRLQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_FR32X }, },
34969   { 14820 /* vpsrlvd */, X86::VPSRLVDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
34971   { 14820 /* vpsrlvd */, X86::VPSRLVDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
34973   { 14820 /* vpsrlvd */, X86::VPSRLVDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35000   { 14828 /* vpsrlvq */, X86::VPSRLVQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35002   { 14828 /* vpsrlvq */, X86::VPSRLVQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35004   { 14828 /* vpsrlvq */, X86::VPSRLVQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35024   { 14836 /* vpsrlvw */, X86::VPSRLVWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35026   { 14836 /* vpsrlvw */, X86::VPSRLVWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35028   { 14836 /* vpsrlvw */, X86::VPSRLVWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35054   { 14844 /* vpsrlw */, X86::VPSRLWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35058   { 14844 /* vpsrlw */, X86::VPSRLWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_FR32X }, },
35062   { 14844 /* vpsrlw */, X86::VPSRLWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_FR32X }, },
35088   { 14851 /* vpsubb */, X86::VPSUBBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35090   { 14851 /* vpsubb */, X86::VPSUBBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35092   { 14851 /* vpsubb */, X86::VPSUBBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35113   { 14858 /* vpsubd */, X86::VPSUBDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35115   { 14858 /* vpsubd */, X86::VPSUBDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35117   { 14858 /* vpsubd */, X86::VPSUBDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35144   { 14865 /* vpsubq */, X86::VPSUBQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35146   { 14865 /* vpsubq */, X86::VPSUBQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35148   { 14865 /* vpsubq */, X86::VPSUBQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35172   { 14872 /* vpsubsb */, X86::VPSUBSBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35174   { 14872 /* vpsubsb */, X86::VPSUBSBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35176   { 14872 /* vpsubsb */, X86::VPSUBSBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35194   { 14880 /* vpsubsw */, X86::VPSUBSWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35196   { 14880 /* vpsubsw */, X86::VPSUBSWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35198   { 14880 /* vpsubsw */, X86::VPSUBSWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35216   { 14888 /* vpsubusb */, X86::VPSUBUSBZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35218   { 14888 /* vpsubusb */, X86::VPSUBUSBZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35220   { 14888 /* vpsubusb */, X86::VPSUBUSBZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35238   { 14897 /* vpsubusw */, X86::VPSUBUSWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35240   { 14897 /* vpsubusw */, X86::VPSUBUSWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35242   { 14897 /* vpsubusw */, X86::VPSUBUSWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35260   { 14906 /* vpsubw */, X86::VPSUBWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35262   { 14906 /* vpsubw */, X86::VPSUBWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35264   { 14906 /* vpsubw */, X86::VPSUBWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35460   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35462   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35464   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35485   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35487   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35489   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35516   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35518   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35520   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35544   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35546   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35548   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35566   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35568   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35570   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35591   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35593   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35595   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35622   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35624   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35626   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35650   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35652   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35654   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35675   { 15114 /* vpxord */, X86::VPXORDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35677   { 15114 /* vpxord */, X86::VPXORDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35679   { 15114 /* vpxord */, X86::VPXORDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35702   { 15121 /* vpxorq */, X86::VPXORQZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35704   { 15121 /* vpxorq */, X86::VPXORQZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
35706   { 15121 /* vpxorq */, X86::VPXORQZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
35854   { 15182 /* vrcp14sd */, X86::VRCP14SDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35860   { 15191 /* vrcp14ss */, X86::VRCP14SSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35891   { 15218 /* vrcp28sd */, X86::VRCP28SDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35895   { 15218 /* vrcp28sd */, X86::VRCP28SDZrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
35900   { 15227 /* vrcp28ss */, X86::VRCP28SSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
35904   { 15227 /* vrcp28ss */, X86::VRCP28SSZrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
36136   { 15396 /* vrsqrt14sd */, X86::VRSQRT14SDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36142   { 15407 /* vrsqrt14ss */, X86::VRSQRT14SSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36173   { 15440 /* vrsqrt28sd */, X86::VRSQRT28SDZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36177   { 15440 /* vrsqrt28sd */, X86::VRSQRT28SDZrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
36182   { 15451 /* vrsqrt28ss */, X86::VRSQRT28SSZrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36186   { 15451 /* vrsqrt28ss */, X86::VRSQRT28SSZrbk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
36204   { 15480 /* vscalefpd */, X86::VSCALEFPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36206   { 15480 /* vscalefpd */, X86::VSCALEFPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36208   { 15480 /* vscalefpd */, X86::VSCALEFPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
36234   { 15490 /* vscalefps */, X86::VSCALEFPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36236   { 15490 /* vscalefps */, X86::VSCALEFPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36238   { 15490 /* vscalefps */, X86::VSCALEFPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
36257   { 15500 /* vscalefsd */, X86::VSCALEFSDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36266   { 15510 /* vscalefss */, X86::VSCALEFSSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36499   { 15764 /* vsqrtsd */, X86::VSQRTSDZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36510   { 15772 /* vsqrtss */, X86::VSQRTSSZr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36531   { 15789 /* vsubpd */, X86::VSUBPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36533   { 15789 /* vsubpd */, X86::VSUBPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36535   { 15789 /* vsubpd */, X86::VSUBPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
36565   { 15796 /* vsubps */, X86::VSUBPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36567   { 15796 /* vsubps */, X86::VSUBPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36569   { 15796 /* vsubps */, X86::VSUBPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
36590   { 15803 /* vsubsd */, X86::VSUBSDZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36601   { 15810 /* vsubss */, X86::VSUBSSZrr_Intk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36638   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36640   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36642   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
36669   { 15861 /* vunpckhps */, X86::VUNPCKHPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36671   { 15861 /* vunpckhps */, X86::VUNPCKHPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36673   { 15861 /* vunpckhps */, X86::VUNPCKHPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
36700   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36702   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36704   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
36731   { 15881 /* vunpcklps */, X86::VUNPCKLPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36733   { 15881 /* vunpcklps */, X86::VUNPCKLPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36735   { 15881 /* vunpcklps */, X86::VUNPCKLPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
36762   { 15891 /* vxorpd */, X86::VXORPDZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36764   { 15891 /* vxorpd */, X86::VXORPDZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36766   { 15891 /* vxorpd */, X86::VXORPDZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },
36793   { 15898 /* vxorps */, X86::VXORPSZ128rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_FR32X, MCK_FR32X }, },
36795   { 15898 /* vxorps */, X86::VXORPSZ256rrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR256X, MCK_VR256X }, },
36797   { 15898 /* vxorps */, X86::VXORPSZrrk, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_4__Reg1_5, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK_VR512, MCK_VR512 }, },