reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

25122   { 8030 /* vaddpd */, X86::VADDPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25125   { 8030 /* vaddpd */, X86::VADDPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
25128   { 8030 /* vaddpd */, X86::VADDPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
25156   { 8037 /* vaddps */, X86::VADDPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25159   { 8037 /* vaddps */, X86::VADDPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
25162   { 8037 /* vaddps */, X86::VADDPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
25177   { 8044 /* vaddsd */, X86::VADDSDZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25188   { 8051 /* vaddss */, X86::VADDSSZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25317   { 8159 /* vandnpd */, X86::VANDNPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25320   { 8159 /* vandnpd */, X86::VANDNPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
25323   { 8159 /* vandnpd */, X86::VANDNPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
25348   { 8167 /* vandnps */, X86::VANDNPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25351   { 8167 /* vandnps */, X86::VANDNPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
25354   { 8167 /* vandnps */, X86::VANDNPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
25379   { 8175 /* vandpd */, X86::VANDPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25382   { 8175 /* vandpd */, X86::VANDPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
25385   { 8175 /* vandpd */, X86::VANDPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
25410   { 8182 /* vandps */, X86::VANDPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25413   { 8182 /* vandps */, X86::VANDPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
25416   { 8182 /* vandps */, X86::VANDPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
25437   { 8189 /* vblendmpd */, X86::VBLENDMPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25440   { 8189 /* vblendmpd */, X86::VBLENDMPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
25443   { 8189 /* vblendmpd */, X86::VBLENDMPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
25464   { 8199 /* vblendmps */, X86::VBLENDMPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25467   { 8199 /* vblendmps */, X86::VBLENDMPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
25470   { 8199 /* vblendmps */, X86::VBLENDMPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
25780   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Z128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
25783   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Z256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
25786   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Zrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
26263   { 8876 /* vcvtsd2ss */, X86::VCVTSD2SSZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
26299   { 8985 /* vcvtss2sd */, X86::VCVTSS2SDZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
26302   { 8985 /* vcvtss2sd */, X86::VCVTSS2SDZrrb_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
26765   { 9498 /* vdivpd */, X86::VDIVPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
26768   { 9498 /* vdivpd */, X86::VDIVPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
26771   { 9498 /* vdivpd */, X86::VDIVPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
26799   { 9505 /* vdivps */, X86::VDIVPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
26802   { 9505 /* vdivps */, X86::VDIVPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
26805   { 9505 /* vdivps */, X86::VDIVPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
26820   { 9512 /* vdivsd */, X86::VDIVSDZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
26831   { 9519 /* vdivss */, X86::VDIVSSZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
28811   { 11095 /* vgetexpsd */, X86::VGETEXPSDZrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
28814   { 11095 /* vgetexpsd */, X86::VGETEXPSDZrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
28820   { 11105 /* vgetexpss */, X86::VGETEXPSSZrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
28823   { 11105 /* vgetexpss */, X86::VGETEXPSSZrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
28980   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
28982   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
28984   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
29115   { 11423 /* vmaxpd */, X86::VMAXPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29118   { 11423 /* vmaxpd */, X86::VMAXPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
29121   { 11423 /* vmaxpd */, X86::VMAXPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
29127   { 11423 /* vmaxpd */, X86::VMAXPDZrrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29149   { 11430 /* vmaxps */, X86::VMAXPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29152   { 11430 /* vmaxps */, X86::VMAXPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
29155   { 11430 /* vmaxps */, X86::VMAXPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
29161   { 11430 /* vmaxps */, X86::VMAXPSZrrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29170   { 11437 /* vmaxsd */, X86::VMAXSDZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29173   { 11437 /* vmaxsd */, X86::VMAXSDZrrb_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29181   { 11444 /* vmaxss */, X86::VMAXSSZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29184   { 11444 /* vmaxss */, X86::VMAXSSZrrb_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29208   { 11473 /* vminpd */, X86::VMINPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29211   { 11473 /* vminpd */, X86::VMINPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
29214   { 11473 /* vminpd */, X86::VMINPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
29220   { 11473 /* vminpd */, X86::VMINPDZrrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29242   { 11480 /* vminps */, X86::VMINPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29245   { 11480 /* vminps */, X86::VMINPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
29248   { 11480 /* vminps */, X86::VMINPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
29254   { 11480 /* vminps */, X86::VMINPSZrrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29263   { 11487 /* vminsd */, X86::VMINSDZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29266   { 11487 /* vminsd */, X86::VMINSDZrrb_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29274   { 11494 /* vminss */, X86::VMINSSZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29277   { 11494 /* vminss */, X86::VMINSSZrrb_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29678   { 11863 /* vmovsd */, X86::VMOVSDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29682   { 11870 /* vmovsd.s */, X86::VMOVSDZrrkz_REV, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29737   { 11899 /* vmovss */, X86::VMOVSSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29741   { 11906 /* vmovss.s */, X86::VMOVSSZrrkz_REV, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29859   { 12021 /* vmulpd */, X86::VMULPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29862   { 12021 /* vmulpd */, X86::VMULPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
29865   { 12021 /* vmulpd */, X86::VMULPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
29893   { 12028 /* vmulps */, X86::VMULPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29896   { 12028 /* vmulps */, X86::VMULPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
29899   { 12028 /* vmulps */, X86::VMULPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
29914   { 12035 /* vmulsd */, X86::VMULSDZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29925   { 12042 /* vmulss */, X86::VMULSSZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29954   { 12088 /* vorpd */, X86::VORPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29957   { 12088 /* vorpd */, X86::VORPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
29960   { 12088 /* vorpd */, X86::VORPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
29985   { 12094 /* vorps */, X86::VORPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
29988   { 12094 /* vorps */, X86::VORPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
29991   { 12094 /* vorps */, X86::VORPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30142   { 12177 /* vpackssdw */, X86::VPACKSSDWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30145   { 12177 /* vpackssdw */, X86::VPACKSSDWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30148   { 12177 /* vpackssdw */, X86::VPACKSSDWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30170   { 12187 /* vpacksswb */, X86::VPACKSSWBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30172   { 12187 /* vpacksswb */, X86::VPACKSSWBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30174   { 12187 /* vpacksswb */, X86::VPACKSSWBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30195   { 12197 /* vpackusdw */, X86::VPACKUSDWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30198   { 12197 /* vpackusdw */, X86::VPACKUSDWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30201   { 12197 /* vpackusdw */, X86::VPACKUSDWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30223   { 12207 /* vpackuswb */, X86::VPACKUSWBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30225   { 12207 /* vpackuswb */, X86::VPACKUSWBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30227   { 12207 /* vpackuswb */, X86::VPACKUSWBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30245   { 12217 /* vpaddb */, X86::VPADDBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30247   { 12217 /* vpaddb */, X86::VPADDBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30249   { 12217 /* vpaddb */, X86::VPADDBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30270   { 12224 /* vpaddd */, X86::VPADDDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30273   { 12224 /* vpaddd */, X86::VPADDDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30276   { 12224 /* vpaddd */, X86::VPADDDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30301   { 12231 /* vpaddq */, X86::VPADDQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30304   { 12231 /* vpaddq */, X86::VPADDQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30307   { 12231 /* vpaddq */, X86::VPADDQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30329   { 12238 /* vpaddsb */, X86::VPADDSBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30331   { 12238 /* vpaddsb */, X86::VPADDSBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30333   { 12238 /* vpaddsb */, X86::VPADDSBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30351   { 12246 /* vpaddsw */, X86::VPADDSWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30353   { 12246 /* vpaddsw */, X86::VPADDSWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30355   { 12246 /* vpaddsw */, X86::VPADDSWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30373   { 12254 /* vpaddusb */, X86::VPADDUSBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30375   { 12254 /* vpaddusb */, X86::VPADDUSBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30377   { 12254 /* vpaddusb */, X86::VPADDUSBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30395   { 12263 /* vpaddusw */, X86::VPADDUSWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30397   { 12263 /* vpaddusw */, X86::VPADDUSWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30399   { 12263 /* vpaddusw */, X86::VPADDUSWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30417   { 12272 /* vpaddw */, X86::VPADDWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30419   { 12272 /* vpaddw */, X86::VPADDWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30421   { 12272 /* vpaddw */, X86::VPADDWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30464   { 12294 /* vpandd */, X86::VPANDDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30467   { 12294 /* vpandd */, X86::VPANDDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30470   { 12294 /* vpandd */, X86::VPANDDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30495   { 12308 /* vpandnd */, X86::VPANDNDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30498   { 12308 /* vpandnd */, X86::VPANDNDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30501   { 12308 /* vpandnd */, X86::VPANDNDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30522   { 12316 /* vpandnq */, X86::VPANDNQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30525   { 12316 /* vpandnq */, X86::VPANDNQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30528   { 12316 /* vpandnq */, X86::VPANDNQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30549   { 12324 /* vpandq */, X86::VPANDQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30552   { 12324 /* vpandq */, X86::VPANDQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30555   { 12324 /* vpandq */, X86::VPANDQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30577   { 12331 /* vpavgb */, X86::VPAVGBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30579   { 12331 /* vpavgb */, X86::VPAVGBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30581   { 12331 /* vpavgb */, X86::VPAVGBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30599   { 12338 /* vpavgw */, X86::VPAVGWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30601   { 12338 /* vpavgw */, X86::VPAVGWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30603   { 12338 /* vpavgw */, X86::VPAVGWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30621   { 12354 /* vpblendmb */, X86::VPBLENDMBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30623   { 12354 /* vpblendmb */, X86::VPBLENDMBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30625   { 12354 /* vpblendmb */, X86::VPBLENDMBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30642   { 12364 /* vpblendmd */, X86::VPBLENDMDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30645   { 12364 /* vpblendmd */, X86::VPBLENDMDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30648   { 12364 /* vpblendmd */, X86::VPBLENDMDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30669   { 12374 /* vpblendmq */, X86::VPBLENDMQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30672   { 12374 /* vpblendmq */, X86::VPBLENDMQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30675   { 12374 /* vpblendmq */, X86::VPBLENDMQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
30693   { 12384 /* vpblendmw */, X86::VPBLENDMWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
30695   { 12384 /* vpblendmw */, X86::VPBLENDMWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
30697   { 12384 /* vpblendmw */, X86::VPBLENDMWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
31427   { 12939 /* vpermb */, X86::VPERMBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
31429   { 12939 /* vpermb */, X86::VPERMBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
31431   { 12939 /* vpermb */, X86::VPERMBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
31445   { 12946 /* vpermd */, X86::VPERMDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
31448   { 12946 /* vpermd */, X86::VPERMDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
31647   { 13031 /* vpermilpd */, X86::VPERMILPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
31653   { 13031 /* vpermilpd */, X86::VPERMILPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
31659   { 13031 /* vpermilpd */, X86::VPERMILPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
31709   { 13041 /* vpermilps */, X86::VPERMILPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
31715   { 13041 /* vpermilps */, X86::VPERMILPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
31721   { 13041 /* vpermilps */, X86::VPERMILPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
31755   { 13051 /* vpermpd */, X86::VPERMPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
31761   { 13051 /* vpermpd */, X86::VPERMPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
31783   { 13059 /* vpermps */, X86::VPERMPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
31786   { 13059 /* vpermps */, X86::VPERMPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
31813   { 13067 /* vpermq */, X86::VPERMQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
31819   { 13067 /* vpermq */, X86::VPERMQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
31985   { 13130 /* vpermw */, X86::VPERMWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
31987   { 13130 /* vpermw */, X86::VPERMWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
31989   { 13130 /* vpermw */, X86::VPERMWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32319   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32321   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32323   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32341   { 13661 /* vpmaddwd */, X86::VPMADDWDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32343   { 13661 /* vpmaddwd */, X86::VPMADDWDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32345   { 13661 /* vpmaddwd */, X86::VPMADDWDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32371   { 13692 /* vpmaxsb */, X86::VPMAXSBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32373   { 13692 /* vpmaxsb */, X86::VPMAXSBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32375   { 13692 /* vpmaxsb */, X86::VPMAXSBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32396   { 13700 /* vpmaxsd */, X86::VPMAXSDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32399   { 13700 /* vpmaxsd */, X86::VPMAXSDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32402   { 13700 /* vpmaxsd */, X86::VPMAXSDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32423   { 13708 /* vpmaxsq */, X86::VPMAXSQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32426   { 13708 /* vpmaxsq */, X86::VPMAXSQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32429   { 13708 /* vpmaxsq */, X86::VPMAXSQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32451   { 13716 /* vpmaxsw */, X86::VPMAXSWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32453   { 13716 /* vpmaxsw */, X86::VPMAXSWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32455   { 13716 /* vpmaxsw */, X86::VPMAXSWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32473   { 13724 /* vpmaxub */, X86::VPMAXUBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32475   { 13724 /* vpmaxub */, X86::VPMAXUBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32477   { 13724 /* vpmaxub */, X86::VPMAXUBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32498   { 13732 /* vpmaxud */, X86::VPMAXUDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32501   { 13732 /* vpmaxud */, X86::VPMAXUDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32504   { 13732 /* vpmaxud */, X86::VPMAXUDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32525   { 13740 /* vpmaxuq */, X86::VPMAXUQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32528   { 13740 /* vpmaxuq */, X86::VPMAXUQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32531   { 13740 /* vpmaxuq */, X86::VPMAXUQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32553   { 13748 /* vpmaxuw */, X86::VPMAXUWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32555   { 13748 /* vpmaxuw */, X86::VPMAXUWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32557   { 13748 /* vpmaxuw */, X86::VPMAXUWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32575   { 13756 /* vpminsb */, X86::VPMINSBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32577   { 13756 /* vpminsb */, X86::VPMINSBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32579   { 13756 /* vpminsb */, X86::VPMINSBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32600   { 13764 /* vpminsd */, X86::VPMINSDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32603   { 13764 /* vpminsd */, X86::VPMINSDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32606   { 13764 /* vpminsd */, X86::VPMINSDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32627   { 13772 /* vpminsq */, X86::VPMINSQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32630   { 13772 /* vpminsq */, X86::VPMINSQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32633   { 13772 /* vpminsq */, X86::VPMINSQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32655   { 13780 /* vpminsw */, X86::VPMINSWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32657   { 13780 /* vpminsw */, X86::VPMINSWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32659   { 13780 /* vpminsw */, X86::VPMINSWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32677   { 13788 /* vpminub */, X86::VPMINUBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32679   { 13788 /* vpminub */, X86::VPMINUBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32681   { 13788 /* vpminub */, X86::VPMINUBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32702   { 13796 /* vpminud */, X86::VPMINUDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32705   { 13796 /* vpminud */, X86::VPMINUDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32708   { 13796 /* vpminud */, X86::VPMINUDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32729   { 13804 /* vpminuq */, X86::VPMINUQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32732   { 13804 /* vpminuq */, X86::VPMINUQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32735   { 13804 /* vpminuq */, X86::VPMINUQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
32757   { 13812 /* vpminuw */, X86::VPMINUWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
32759   { 13812 /* vpminuw */, X86::VPMINUWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
32761   { 13812 /* vpminuw */, X86::VPMINUWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33342   { 14184 /* vpmuldq */, X86::VPMULDQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33345   { 14184 /* vpmuldq */, X86::VPMULDQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33348   { 14184 /* vpmuldq */, X86::VPMULDQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33370   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33372   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33374   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33392   { 14202 /* vpmulhuw */, X86::VPMULHUWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33394   { 14202 /* vpmulhuw */, X86::VPMULHUWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33396   { 14202 /* vpmulhuw */, X86::VPMULHUWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33414   { 14211 /* vpmulhw */, X86::VPMULHWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33416   { 14211 /* vpmulhw */, X86::VPMULHWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33418   { 14211 /* vpmulhw */, X86::VPMULHWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33439   { 14219 /* vpmulld */, X86::VPMULLDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33442   { 14219 /* vpmulld */, X86::VPMULLDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33445   { 14219 /* vpmulld */, X86::VPMULLDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33466   { 14227 /* vpmullq */, X86::VPMULLQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33469   { 14227 /* vpmullq */, X86::VPMULLQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33472   { 14227 /* vpmullq */, X86::VPMULLQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33494   { 14235 /* vpmullw */, X86::VPMULLWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33496   { 14235 /* vpmullw */, X86::VPMULLWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33498   { 14235 /* vpmullw */, X86::VPMULLWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33515   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33518   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33521   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33546   { 14258 /* vpmuludq */, X86::VPMULUDQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33549   { 14258 /* vpmuludq */, X86::VPMULUDQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33552   { 14258 /* vpmuludq */, X86::VPMULUDQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33667   { 14308 /* vpord */, X86::VPORDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33670   { 14308 /* vpord */, X86::VPORDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33673   { 14308 /* vpord */, X86::VPORDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33694   { 14314 /* vporq */, X86::VPORQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33697   { 14314 /* vporq */, X86::VPORQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33700   { 14314 /* vporq */, X86::VPORQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33778   { 14341 /* vprolvd */, X86::VPROLVDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33781   { 14341 /* vprolvd */, X86::VPROLVDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33784   { 14341 /* vprolvd */, X86::VPROLVDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33805   { 14349 /* vprolvq */, X86::VPROLVQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33808   { 14349 /* vprolvq */, X86::VPROLVQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33811   { 14349 /* vprolvq */, X86::VPROLVQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33886   { 14371 /* vprorvd */, X86::VPRORVDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33889   { 14371 /* vprorvd */, X86::VPRORVDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33892   { 14371 /* vprorvd */, X86::VPRORVDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
33913   { 14379 /* vprorvq */, X86::VPRORVQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
33916   { 14379 /* vprorvq */, X86::VPRORVQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
33919   { 14379 /* vprorvq */, X86::VPRORVQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
34295   { 14629 /* vpshufb */, X86::VPSHUFBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34297   { 14629 /* vpshufb */, X86::VPSHUFBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
34299   { 14629 /* vpshufb */, X86::VPSHUFBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
34433   { 14700 /* vpslld */, X86::VPSLLDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34438   { 14700 /* vpslld */, X86::VPSLLDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_FR32X }, },
34443   { 14700 /* vpslld */, X86::VPSLLDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_FR32X }, },
34492   { 14715 /* vpsllq */, X86::VPSLLQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34497   { 14715 /* vpsllq */, X86::VPSLLQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_FR32X }, },
34502   { 14715 /* vpsllq */, X86::VPSLLQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_FR32X }, },
34529   { 14722 /* vpsllvd */, X86::VPSLLVDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34532   { 14722 /* vpsllvd */, X86::VPSLLVDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
34535   { 14722 /* vpsllvd */, X86::VPSLLVDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
34560   { 14730 /* vpsllvq */, X86::VPSLLVQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34563   { 14730 /* vpsllvq */, X86::VPSLLVQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
34566   { 14730 /* vpsllvq */, X86::VPSLLVQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
34584   { 14738 /* vpsllvw */, X86::VPSLLVWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34586   { 14738 /* vpsllvw */, X86::VPSLLVWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
34588   { 14738 /* vpsllvw */, X86::VPSLLVWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
34620   { 14746 /* vpsllw */, X86::VPSLLWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34624   { 14746 /* vpsllw */, X86::VPSLLWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_FR32X }, },
34628   { 14746 /* vpsllw */, X86::VPSLLWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_FR32X }, },
34665   { 14753 /* vpsrad */, X86::VPSRADZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34670   { 14753 /* vpsrad */, X86::VPSRADZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_FR32X }, },
34675   { 14753 /* vpsrad */, X86::VPSRADZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_FR32X }, },
34710   { 14760 /* vpsraq */, X86::VPSRAQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34715   { 14760 /* vpsraq */, X86::VPSRAQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_FR32X }, },
34720   { 14760 /* vpsraq */, X86::VPSRAQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_FR32X }, },
34747   { 14767 /* vpsravd */, X86::VPSRAVDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34750   { 14767 /* vpsravd */, X86::VPSRAVDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
34753   { 14767 /* vpsravd */, X86::VPSRAVDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
34774   { 14775 /* vpsravq */, X86::VPSRAVQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34777   { 14775 /* vpsravq */, X86::VPSRAVQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
34780   { 14775 /* vpsravq */, X86::VPSRAVQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
34798   { 14783 /* vpsravw */, X86::VPSRAVWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34800   { 14783 /* vpsravw */, X86::VPSRAVWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
34802   { 14783 /* vpsravw */, X86::VPSRAVWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
34834   { 14791 /* vpsraw */, X86::VPSRAWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34838   { 14791 /* vpsraw */, X86::VPSRAWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_FR32X }, },
34842   { 14791 /* vpsraw */, X86::VPSRAWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_FR32X }, },
34879   { 14798 /* vpsrld */, X86::VPSRLDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34884   { 14798 /* vpsrld */, X86::VPSRLDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_FR32X }, },
34889   { 14798 /* vpsrld */, X86::VPSRLDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_FR32X }, },
34938   { 14813 /* vpsrlq */, X86::VPSRLQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34943   { 14813 /* vpsrlq */, X86::VPSRLQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_FR32X }, },
34948   { 14813 /* vpsrlq */, X86::VPSRLQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_FR32X }, },
34975   { 14820 /* vpsrlvd */, X86::VPSRLVDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
34978   { 14820 /* vpsrlvd */, X86::VPSRLVDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
34981   { 14820 /* vpsrlvd */, X86::VPSRLVDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35006   { 14828 /* vpsrlvq */, X86::VPSRLVQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35009   { 14828 /* vpsrlvq */, X86::VPSRLVQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35012   { 14828 /* vpsrlvq */, X86::VPSRLVQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35030   { 14836 /* vpsrlvw */, X86::VPSRLVWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35032   { 14836 /* vpsrlvw */, X86::VPSRLVWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35034   { 14836 /* vpsrlvw */, X86::VPSRLVWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35066   { 14844 /* vpsrlw */, X86::VPSRLWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35070   { 14844 /* vpsrlw */, X86::VPSRLWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_FR32X }, },
35074   { 14844 /* vpsrlw */, X86::VPSRLWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_FR32X }, },
35094   { 14851 /* vpsubb */, X86::VPSUBBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35096   { 14851 /* vpsubb */, X86::VPSUBBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35098   { 14851 /* vpsubb */, X86::VPSUBBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35119   { 14858 /* vpsubd */, X86::VPSUBDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35122   { 14858 /* vpsubd */, X86::VPSUBDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35125   { 14858 /* vpsubd */, X86::VPSUBDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35150   { 14865 /* vpsubq */, X86::VPSUBQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35153   { 14865 /* vpsubq */, X86::VPSUBQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35156   { 14865 /* vpsubq */, X86::VPSUBQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35178   { 14872 /* vpsubsb */, X86::VPSUBSBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35180   { 14872 /* vpsubsb */, X86::VPSUBSBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35182   { 14872 /* vpsubsb */, X86::VPSUBSBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35200   { 14880 /* vpsubsw */, X86::VPSUBSWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35202   { 14880 /* vpsubsw */, X86::VPSUBSWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35204   { 14880 /* vpsubsw */, X86::VPSUBSWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35222   { 14888 /* vpsubusb */, X86::VPSUBUSBZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35224   { 14888 /* vpsubusb */, X86::VPSUBUSBZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35226   { 14888 /* vpsubusb */, X86::VPSUBUSBZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35244   { 14897 /* vpsubusw */, X86::VPSUBUSWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35246   { 14897 /* vpsubusw */, X86::VPSUBUSWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35248   { 14897 /* vpsubusw */, X86::VPSUBUSWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35266   { 14906 /* vpsubw */, X86::VPSUBWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35268   { 14906 /* vpsubw */, X86::VPSUBWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35270   { 14906 /* vpsubw */, X86::VPSUBWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35466   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35468   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35470   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35491   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35494   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35497   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35522   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35525   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35528   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35550   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35552   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35554   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35572   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35574   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35576   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35597   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35600   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35603   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35628   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35631   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35634   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35656   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35658   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35660   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35681   { 15114 /* vpxord */, X86::VPXORDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35684   { 15114 /* vpxord */, X86::VPXORDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35687   { 15114 /* vpxord */, X86::VPXORDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35708   { 15121 /* vpxorq */, X86::VPXORQZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35711   { 15121 /* vpxorq */, X86::VPXORQZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
35714   { 15121 /* vpxorq */, X86::VPXORQZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
35856   { 15182 /* vrcp14sd */, X86::VRCP14SDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35862   { 15191 /* vrcp14ss */, X86::VRCP14SSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35893   { 15218 /* vrcp28sd */, X86::VRCP28SDZrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35896   { 15218 /* vrcp28sd */, X86::VRCP28SDZrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
35902   { 15227 /* vrcp28ss */, X86::VRCP28SSZrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
35905   { 15227 /* vrcp28ss */, X86::VRCP28SSZrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
36138   { 15396 /* vrsqrt14sd */, X86::VRSQRT14SDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36144   { 15407 /* vrsqrt14ss */, X86::VRSQRT14SSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36175   { 15440 /* vrsqrt28sd */, X86::VRSQRT28SDZrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36178   { 15440 /* vrsqrt28sd */, X86::VRSQRT28SDZrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
36184   { 15451 /* vrsqrt28ss */, X86::VRSQRT28SSZrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36187   { 15451 /* vrsqrt28ss */, X86::VRSQRT28SSZrbkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
36210   { 15480 /* vscalefpd */, X86::VSCALEFPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36213   { 15480 /* vscalefpd */, X86::VSCALEFPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36216   { 15480 /* vscalefpd */, X86::VSCALEFPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
36240   { 15490 /* vscalefps */, X86::VSCALEFPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36243   { 15490 /* vscalefps */, X86::VSCALEFPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36246   { 15490 /* vscalefps */, X86::VSCALEFPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
36259   { 15500 /* vscalefsd */, X86::VSCALEFSDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36268   { 15510 /* vscalefss */, X86::VSCALEFSSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36501   { 15764 /* vsqrtsd */, X86::VSQRTSDZr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36512   { 15772 /* vsqrtss */, X86::VSQRTSSZr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36537   { 15789 /* vsubpd */, X86::VSUBPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36540   { 15789 /* vsubpd */, X86::VSUBPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36543   { 15789 /* vsubpd */, X86::VSUBPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
36571   { 15796 /* vsubps */, X86::VSUBPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36574   { 15796 /* vsubps */, X86::VSUBPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36577   { 15796 /* vsubps */, X86::VSUBPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
36592   { 15803 /* vsubsd */, X86::VSUBSDZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36603   { 15810 /* vsubss */, X86::VSUBSSZrr_Intkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36644   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36647   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36650   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
36675   { 15861 /* vunpckhps */, X86::VUNPCKHPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36678   { 15861 /* vunpckhps */, X86::VUNPCKHPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36681   { 15861 /* vunpckhps */, X86::VUNPCKHPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
36706   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36709   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36712   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
36737   { 15881 /* vunpcklps */, X86::VUNPCKLPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36740   { 15881 /* vunpcklps */, X86::VUNPCKLPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36743   { 15881 /* vunpcklps */, X86::VUNPCKLPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
36768   { 15891 /* vxorpd */, X86::VXORPDZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36771   { 15891 /* vxorpd */, X86::VXORPDZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36774   { 15891 /* vxorpd */, X86::VXORPDZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },
36799   { 15898 /* vxorps */, X86::VXORPSZ128rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_FR32X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_FR32X, MCK_FR32X }, },
36802   { 15898 /* vxorps */, X86::VXORPSZ256rrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR256X, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR256X, MCK_VR256X }, },
36805   { 15898 /* vxorps */, X86::VXORPSZrrkz, Convert__Reg1_0__Reg1_2__Reg1_5__Reg1_6, AMFBS_None, { MCK_VR512, MCK__123_, MCK_VK16WM, MCK__125_, MCK__123_z_125_, MCK_VR512, MCK_VR512 }, },