reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

22694   { 213 /* andn */, X86::ANDN32rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
22696   { 213 /* andn */, X86::ANDN64rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
22708   { 271 /* bextr */, X86::BEXTR32rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
22712   { 271 /* bextr */, X86::BEXTR64rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
22853   { 712 /* bzhi */, X86::BZHI32rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
22855   { 712 /* bzhi */, X86::BZHI64rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
23525   { 3437 /* kaddb */, X86::KADDBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23526   { 3443 /* kaddd */, X86::KADDDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23527   { 3449 /* kaddq */, X86::KADDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23528   { 3455 /* kaddw */, X86::KADDWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23529   { 3461 /* kandb */, X86::KANDBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23530   { 3467 /* kandd */, X86::KANDDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23531   { 3473 /* kandnb */, X86::KANDNBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23532   { 3480 /* kandnd */, X86::KANDNDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23533   { 3487 /* kandnq */, X86::KANDNQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23534   { 3494 /* kandnw */, X86::KANDNWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23535   { 3501 /* kandq */, X86::KANDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23536   { 3507 /* kandw */, X86::KANDWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23561   { 3561 /* korb */, X86::KORBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23562   { 3566 /* kord */, X86::KORDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23563   { 3571 /* korq */, X86::KORQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23568   { 3612 /* korw */, X86::KORWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23581   { 3717 /* kunpckbw */, X86::KUNPCKBWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23582   { 3726 /* kunpckdq */, X86::KUNPCKDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23583   { 3735 /* kunpckwd */, X86::KUNPCKWDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23584   { 3744 /* kxnorb */, X86::KXNORBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23585   { 3751 /* kxnord */, X86::KXNORDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23586   { 3758 /* kxnorq */, X86::KXNORQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23587   { 3765 /* kxnorw */, X86::KXNORWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23588   { 3772 /* kxorb */, X86::KXORBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23589   { 3778 /* kxord */, X86::KXORDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23590   { 3784 /* kxorq */, X86::KXORQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23591   { 3790 /* kxorw */, X86::KXORWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VK1, MCK_VK1 }, },
23924   { 4968 /* mulx */, X86::MULX32rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
23926   { 4968 /* mulx */, X86::MULX64rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
24146   { 5486 /* pdep */, X86::PDEP32rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
24148   { 5486 /* pdep */, X86::PDEP64rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
24150   { 5503 /* pext */, X86::PEXT32rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
24152   { 5503 /* pext */, X86::PEXT64rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
24732   { 7045 /* sarx */, X86::SARX32rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
24734   { 7045 /* sarx */, X86::SARX64rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
24881   { 7385 /* shlx */, X86::SHLX32rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
24883   { 7385 /* shlx */, X86::SHLX64rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
24927   { 7449 /* shrx */, X86::SHRX32rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR32, MCK_GR32, MCK_GR32 }, },
24929   { 7449 /* shrx */, X86::SHRX64rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GR64, MCK_GR64, MCK_GR64 }, },
25102   { 8030 /* vaddpd */, X86::VADDPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25104   { 8030 /* vaddpd */, X86::VADDPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25106   { 8030 /* vaddpd */, X86::VADDPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25108   { 8030 /* vaddpd */, X86::VADDPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25110   { 8030 /* vaddpd */, X86::VADDPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25136   { 8037 /* vaddps */, X86::VADDPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25138   { 8037 /* vaddps */, X86::VADDPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25140   { 8037 /* vaddps */, X86::VADDPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25142   { 8037 /* vaddps */, X86::VADDPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25144   { 8037 /* vaddps */, X86::VADDPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25170   { 8044 /* vaddsd */, X86::VADDSDrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25172   { 8044 /* vaddsd */, X86::VADDSDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25181   { 8051 /* vaddss */, X86::VADDSSrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25183   { 8051 /* vaddss */, X86::VADDSSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25192   { 8058 /* vaddsubpd */, X86::VADDSUBPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25194   { 8058 /* vaddsubpd */, X86::VADDSUBPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25196   { 8068 /* vaddsubps */, X86::VADDSUBPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25198   { 8068 /* vaddsubps */, X86::VADDSUBPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25200   { 8078 /* vaesdec */, X86::VAESDECrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25202   { 8078 /* vaesdec */, X86::VAESDECYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25204   { 8078 /* vaesdec */, X86::VAESDECZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25206   { 8078 /* vaesdec */, X86::VAESDECZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25208   { 8078 /* vaesdec */, X86::VAESDECZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25210   { 8086 /* vaesdeclast */, X86::VAESDECLASTrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25212   { 8086 /* vaesdeclast */, X86::VAESDECLASTYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25214   { 8086 /* vaesdeclast */, X86::VAESDECLASTZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25216   { 8086 /* vaesdeclast */, X86::VAESDECLASTZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25218   { 8086 /* vaesdeclast */, X86::VAESDECLASTZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25220   { 8098 /* vaesenc */, X86::VAESENCrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25222   { 8098 /* vaesenc */, X86::VAESENCYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25224   { 8098 /* vaesenc */, X86::VAESENCZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25226   { 8098 /* vaesenc */, X86::VAESENCZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25228   { 8098 /* vaesenc */, X86::VAESENCZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25230   { 8106 /* vaesenclast */, X86::VAESENCLASTrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25232   { 8106 /* vaesenclast */, X86::VAESENCLASTYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25234   { 8106 /* vaesenclast */, X86::VAESENCLASTZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25236   { 8106 /* vaesenclast */, X86::VAESENCLASTZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25238   { 8106 /* vaesenclast */, X86::VAESENCLASTZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25298   { 8159 /* vandnpd */, X86::VANDNPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25300   { 8159 /* vandnpd */, X86::VANDNPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25302   { 8159 /* vandnpd */, X86::VANDNPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25304   { 8159 /* vandnpd */, X86::VANDNPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25306   { 8159 /* vandnpd */, X86::VANDNPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25329   { 8167 /* vandnps */, X86::VANDNPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25331   { 8167 /* vandnps */, X86::VANDNPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25333   { 8167 /* vandnps */, X86::VANDNPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25335   { 8167 /* vandnps */, X86::VANDNPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25337   { 8167 /* vandnps */, X86::VANDNPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25360   { 8175 /* vandpd */, X86::VANDPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25362   { 8175 /* vandpd */, X86::VANDPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25364   { 8175 /* vandpd */, X86::VANDPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25366   { 8175 /* vandpd */, X86::VANDPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25368   { 8175 /* vandpd */, X86::VANDPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25391   { 8182 /* vandps */, X86::VANDPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
25393   { 8182 /* vandps */, X86::VANDPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
25395   { 8182 /* vandps */, X86::VANDPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25397   { 8182 /* vandps */, X86::VANDPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25399   { 8182 /* vandps */, X86::VANDPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25422   { 8189 /* vblendmpd */, X86::VBLENDMPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25424   { 8189 /* vblendmpd */, X86::VBLENDMPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25426   { 8189 /* vblendmpd */, X86::VBLENDMPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25449   { 8199 /* vblendmps */, X86::VBLENDMPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25451   { 8199 /* vblendmps */, X86::VBLENDMPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25453   { 8199 /* vblendmps */, X86::VBLENDMPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
25765   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Z128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
25767   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Z256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
25769   { 8551 /* vcvtne2ps2bf16 */, X86::VCVTNE2PS2BF16Zrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
26256   { 8876 /* vcvtsd2ss */, X86::VCVTSD2SSrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
26258   { 8876 /* vcvtsd2ss */, X86::VCVTSD2SSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
26273   { 8921 /* vcvtsi2sd */, X86::VCVTSI2SDrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_GR32 }, },
26274   { 8921 /* vcvtsi2sd */, X86::VCVTSI642SDrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_GR64 }, },
26277   { 8921 /* vcvtsi2sd */, X86::VCVTSI2SDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_GR32 }, },
26278   { 8921 /* vcvtsi2sd */, X86::VCVTSI642SDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_GR64 }, },
26282   { 8953 /* vcvtsi2ss */, X86::VCVTSI2SSrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_GR32 }, },
26283   { 8953 /* vcvtsi2ss */, X86::VCVTSI642SSrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_GR64 }, },
26286   { 8953 /* vcvtsi2ss */, X86::VCVTSI2SSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_GR32 }, },
26287   { 8953 /* vcvtsi2ss */, X86::VCVTSI642SSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_GR64 }, },
26292   { 8985 /* vcvtss2sd */, X86::VCVTSS2SDrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
26294   { 8985 /* vcvtss2sd */, X86::VCVTSS2SDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
26296   { 8985 /* vcvtss2sd */, X86::VCVTSS2SDZrrb_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
26716   { 9418 /* vcvtusi2sd */, X86::VCVTUSI2SDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_GR32 }, },
26717   { 9418 /* vcvtusi2sd */, X86::VCVTUSI642SDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_GR64 }, },
26721   { 9453 /* vcvtusi2ss */, X86::VCVTUSI2SSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_GR32 }, },
26722   { 9453 /* vcvtusi2ss */, X86::VCVTUSI642SSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_GR64 }, },
26745   { 9498 /* vdivpd */, X86::VDIVPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
26747   { 9498 /* vdivpd */, X86::VDIVPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
26749   { 9498 /* vdivpd */, X86::VDIVPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
26751   { 9498 /* vdivpd */, X86::VDIVPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
26753   { 9498 /* vdivpd */, X86::VDIVPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
26779   { 9505 /* vdivps */, X86::VDIVPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
26781   { 9505 /* vdivps */, X86::VDIVPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
26783   { 9505 /* vdivps */, X86::VDIVPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
26785   { 9505 /* vdivps */, X86::VDIVPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
26787   { 9505 /* vdivps */, X86::VDIVPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
26813   { 9512 /* vdivsd */, X86::VDIVSDrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
26815   { 9512 /* vdivsd */, X86::VDIVSDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
26824   { 9519 /* vdivss */, X86::VDIVSSrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
26826   { 9519 /* vdivss */, X86::VDIVSSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
28806   { 11095 /* vgetexpsd */, X86::VGETEXPSDZr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
28808   { 11095 /* vgetexpsd */, X86::VGETEXPSDZrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
28815   { 11105 /* vgetexpss */, X86::VGETEXPSSZr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
28817   { 11105 /* vgetexpss */, X86::VGETEXPSSZrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
28964   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
28966   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
28968   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
28970   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
28972   { 11192 /* vgf2p8mulb */, X86::VGF2P8MULBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
28986   { 11203 /* vhaddpd */, X86::VHADDPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
28988   { 11203 /* vhaddpd */, X86::VHADDPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
28990   { 11211 /* vhaddps */, X86::VHADDPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
28992   { 11211 /* vhaddps */, X86::VHADDPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
28994   { 11219 /* vhsubpd */, X86::VHSUBPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
28996   { 11219 /* vhsubpd */, X86::VHSUBPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
28998   { 11227 /* vhsubps */, X86::VHSUBPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29000   { 11227 /* vhsubps */, X86::VHSUBPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
29095   { 11423 /* vmaxpd */, X86::VMAXPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29097   { 11423 /* vmaxpd */, X86::VMAXPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
29099   { 11423 /* vmaxpd */, X86::VMAXPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29101   { 11423 /* vmaxpd */, X86::VMAXPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
29103   { 11423 /* vmaxpd */, X86::VMAXPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
29107   { 11423 /* vmaxpd */, X86::VMAXPDZrrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29129   { 11430 /* vmaxps */, X86::VMAXPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29131   { 11430 /* vmaxps */, X86::VMAXPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
29133   { 11430 /* vmaxps */, X86::VMAXPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29135   { 11430 /* vmaxps */, X86::VMAXPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
29137   { 11430 /* vmaxps */, X86::VMAXPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
29141   { 11430 /* vmaxps */, X86::VMAXPSZrrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29163   { 11437 /* vmaxsd */, X86::VMAXSDrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29165   { 11437 /* vmaxsd */, X86::VMAXSDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29167   { 11437 /* vmaxsd */, X86::VMAXSDZrrb_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29174   { 11444 /* vmaxss */, X86::VMAXSSrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29176   { 11444 /* vmaxss */, X86::VMAXSSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29178   { 11444 /* vmaxss */, X86::VMAXSSZrrb_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29188   { 11473 /* vminpd */, X86::VMINPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29190   { 11473 /* vminpd */, X86::VMINPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
29192   { 11473 /* vminpd */, X86::VMINPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29194   { 11473 /* vminpd */, X86::VMINPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
29196   { 11473 /* vminpd */, X86::VMINPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
29200   { 11473 /* vminpd */, X86::VMINPDZrrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29222   { 11480 /* vminps */, X86::VMINPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29224   { 11480 /* vminps */, X86::VMINPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
29226   { 11480 /* vminps */, X86::VMINPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29228   { 11480 /* vminps */, X86::VMINPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
29230   { 11480 /* vminps */, X86::VMINPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
29234   { 11480 /* vminps */, X86::VMINPSZrrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512, MCK__123_sae_125_ }, },
29256   { 11487 /* vminsd */, X86::VMINSDrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29258   { 11487 /* vminsd */, X86::VMINSDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29260   { 11487 /* vminsd */, X86::VMINSDZrrb_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29267   { 11494 /* vminss */, X86::VMINSSrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29269   { 11494 /* vminss */, X86::VMINSSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29271   { 11494 /* vminss */, X86::VMINSSZrrb_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
29612   { 11742 /* vmovhlps */, X86::VMOVHLPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29613   { 11742 /* vmovhlps */, X86::VMOVHLPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29622   { 11767 /* vmovlhps */, X86::VMOVLHPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29623   { 11767 /* vmovlhps */, X86::VMOVLHPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29672   { 11863 /* vmovsd */, X86::VMOVSDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29673   { 11863 /* vmovsd */, X86::VMOVSDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29679   { 11870 /* vmovsd.s */, X86::VMOVSDrr_REV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29680   { 11870 /* vmovsd.s */, X86::VMOVSDZrr_REV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29731   { 11899 /* vmovss */, X86::VMOVSSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29732   { 11899 /* vmovss */, X86::VMOVSSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29738   { 11906 /* vmovss.s */, X86::VMOVSSrr_REV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29739   { 11906 /* vmovss.s */, X86::VMOVSSZrr_REV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29839   { 12021 /* vmulpd */, X86::VMULPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29841   { 12021 /* vmulpd */, X86::VMULPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
29843   { 12021 /* vmulpd */, X86::VMULPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29845   { 12021 /* vmulpd */, X86::VMULPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
29847   { 12021 /* vmulpd */, X86::VMULPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
29873   { 12028 /* vmulps */, X86::VMULPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29875   { 12028 /* vmulps */, X86::VMULPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
29877   { 12028 /* vmulps */, X86::VMULPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29879   { 12028 /* vmulps */, X86::VMULPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
29881   { 12028 /* vmulps */, X86::VMULPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
29907   { 12035 /* vmulsd */, X86::VMULSDrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29909   { 12035 /* vmulsd */, X86::VMULSDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29918   { 12042 /* vmulss */, X86::VMULSSrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29920   { 12042 /* vmulss */, X86::VMULSSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29935   { 12088 /* vorpd */, X86::VORPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29937   { 12088 /* vorpd */, X86::VORPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
29939   { 12088 /* vorpd */, X86::VORPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29941   { 12088 /* vorpd */, X86::VORPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
29943   { 12088 /* vorpd */, X86::VORPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
29966   { 12094 /* vorps */, X86::VORPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
29968   { 12094 /* vorps */, X86::VORPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
29970   { 12094 /* vorps */, X86::VORPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
29972   { 12094 /* vorps */, X86::VORPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
29974   { 12094 /* vorps */, X86::VORPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30123   { 12177 /* vpackssdw */, X86::VPACKSSDWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30125   { 12177 /* vpackssdw */, X86::VPACKSSDWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30127   { 12177 /* vpackssdw */, X86::VPACKSSDWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30129   { 12177 /* vpackssdw */, X86::VPACKSSDWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30131   { 12177 /* vpackssdw */, X86::VPACKSSDWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30154   { 12187 /* vpacksswb */, X86::VPACKSSWBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30156   { 12187 /* vpacksswb */, X86::VPACKSSWBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30158   { 12187 /* vpacksswb */, X86::VPACKSSWBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30160   { 12187 /* vpacksswb */, X86::VPACKSSWBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30162   { 12187 /* vpacksswb */, X86::VPACKSSWBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30176   { 12197 /* vpackusdw */, X86::VPACKUSDWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30178   { 12197 /* vpackusdw */, X86::VPACKUSDWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30180   { 12197 /* vpackusdw */, X86::VPACKUSDWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30182   { 12197 /* vpackusdw */, X86::VPACKUSDWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30184   { 12197 /* vpackusdw */, X86::VPACKUSDWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30207   { 12207 /* vpackuswb */, X86::VPACKUSWBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30209   { 12207 /* vpackuswb */, X86::VPACKUSWBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30211   { 12207 /* vpackuswb */, X86::VPACKUSWBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30213   { 12207 /* vpackuswb */, X86::VPACKUSWBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30215   { 12207 /* vpackuswb */, X86::VPACKUSWBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30229   { 12217 /* vpaddb */, X86::VPADDBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30231   { 12217 /* vpaddb */, X86::VPADDBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30233   { 12217 /* vpaddb */, X86::VPADDBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30235   { 12217 /* vpaddb */, X86::VPADDBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30237   { 12217 /* vpaddb */, X86::VPADDBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30251   { 12224 /* vpaddd */, X86::VPADDDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30253   { 12224 /* vpaddd */, X86::VPADDDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30255   { 12224 /* vpaddd */, X86::VPADDDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30257   { 12224 /* vpaddd */, X86::VPADDDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30259   { 12224 /* vpaddd */, X86::VPADDDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30282   { 12231 /* vpaddq */, X86::VPADDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30284   { 12231 /* vpaddq */, X86::VPADDQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30286   { 12231 /* vpaddq */, X86::VPADDQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30288   { 12231 /* vpaddq */, X86::VPADDQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30290   { 12231 /* vpaddq */, X86::VPADDQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30313   { 12238 /* vpaddsb */, X86::VPADDSBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30315   { 12238 /* vpaddsb */, X86::VPADDSBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30317   { 12238 /* vpaddsb */, X86::VPADDSBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30319   { 12238 /* vpaddsb */, X86::VPADDSBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30321   { 12238 /* vpaddsb */, X86::VPADDSBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30335   { 12246 /* vpaddsw */, X86::VPADDSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30337   { 12246 /* vpaddsw */, X86::VPADDSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30339   { 12246 /* vpaddsw */, X86::VPADDSWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30341   { 12246 /* vpaddsw */, X86::VPADDSWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30343   { 12246 /* vpaddsw */, X86::VPADDSWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30357   { 12254 /* vpaddusb */, X86::VPADDUSBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30359   { 12254 /* vpaddusb */, X86::VPADDUSBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30361   { 12254 /* vpaddusb */, X86::VPADDUSBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30363   { 12254 /* vpaddusb */, X86::VPADDUSBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30365   { 12254 /* vpaddusb */, X86::VPADDUSBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30379   { 12263 /* vpaddusw */, X86::VPADDUSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30381   { 12263 /* vpaddusw */, X86::VPADDUSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30383   { 12263 /* vpaddusw */, X86::VPADDUSWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30385   { 12263 /* vpaddusw */, X86::VPADDUSWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30387   { 12263 /* vpaddusw */, X86::VPADDUSWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30401   { 12272 /* vpaddw */, X86::VPADDWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30403   { 12272 /* vpaddw */, X86::VPADDWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30405   { 12272 /* vpaddw */, X86::VPADDWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30407   { 12272 /* vpaddw */, X86::VPADDWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30409   { 12272 /* vpaddw */, X86::VPADDWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30445   { 12288 /* vpand */, X86::VPANDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30447   { 12288 /* vpand */, X86::VPANDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30449   { 12294 /* vpandd */, X86::VPANDDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30451   { 12294 /* vpandd */, X86::VPANDDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30453   { 12294 /* vpandd */, X86::VPANDDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30476   { 12301 /* vpandn */, X86::VPANDNrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30478   { 12301 /* vpandn */, X86::VPANDNYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30480   { 12308 /* vpandnd */, X86::VPANDNDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30482   { 12308 /* vpandnd */, X86::VPANDNDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30484   { 12308 /* vpandnd */, X86::VPANDNDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30507   { 12316 /* vpandnq */, X86::VPANDNQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30509   { 12316 /* vpandnq */, X86::VPANDNQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30511   { 12316 /* vpandnq */, X86::VPANDNQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30534   { 12324 /* vpandq */, X86::VPANDQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30536   { 12324 /* vpandq */, X86::VPANDQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30538   { 12324 /* vpandq */, X86::VPANDQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30561   { 12331 /* vpavgb */, X86::VPAVGBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30563   { 12331 /* vpavgb */, X86::VPAVGBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30565   { 12331 /* vpavgb */, X86::VPAVGBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30567   { 12331 /* vpavgb */, X86::VPAVGBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30569   { 12331 /* vpavgb */, X86::VPAVGBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30583   { 12338 /* vpavgw */, X86::VPAVGWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30585   { 12338 /* vpavgw */, X86::VPAVGWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30587   { 12338 /* vpavgw */, X86::VPAVGWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30589   { 12338 /* vpavgw */, X86::VPAVGWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30591   { 12338 /* vpavgw */, X86::VPAVGWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30609   { 12354 /* vpblendmb */, X86::VPBLENDMBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30611   { 12354 /* vpblendmb */, X86::VPBLENDMBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30613   { 12354 /* vpblendmb */, X86::VPBLENDMBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30627   { 12364 /* vpblendmd */, X86::VPBLENDMDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30629   { 12364 /* vpblendmd */, X86::VPBLENDMDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30631   { 12364 /* vpblendmd */, X86::VPBLENDMDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30654   { 12374 /* vpblendmq */, X86::VPBLENDMQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30656   { 12374 /* vpblendmq */, X86::VPBLENDMQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30658   { 12374 /* vpblendmq */, X86::VPBLENDMQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30681   { 12384 /* vpblendmw */, X86::VPBLENDMWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
30683   { 12384 /* vpblendmw */, X86::VPBLENDMWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
30685   { 12384 /* vpblendmw */, X86::VPBLENDMWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
30923   { 12585 /* vpcmpeqb */, X86::VPCMPEQBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
30925   { 12585 /* vpcmpeqb */, X86::VPCMPEQBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
30927   { 12585 /* vpcmpeqb */, X86::VPCMPEQBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
30929   { 12585 /* vpcmpeqb */, X86::VPCMPEQBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30931   { 12585 /* vpcmpeqb */, X86::VPCMPEQBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30939   { 12594 /* vpcmpeqd */, X86::VPCMPEQDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
30941   { 12594 /* vpcmpeqd */, X86::VPCMPEQDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
30943   { 12594 /* vpcmpeqd */, X86::VPCMPEQDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
30945   { 12594 /* vpcmpeqd */, X86::VPCMPEQDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30947   { 12594 /* vpcmpeqd */, X86::VPCMPEQDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30961   { 12603 /* vpcmpeqq */, X86::VPCMPEQQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
30963   { 12603 /* vpcmpeqq */, X86::VPCMPEQQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
30965   { 12603 /* vpcmpeqq */, X86::VPCMPEQQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
30967   { 12603 /* vpcmpeqq */, X86::VPCMPEQQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30969   { 12603 /* vpcmpeqq */, X86::VPCMPEQQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
30983   { 12612 /* vpcmpeqw */, X86::VPCMPEQWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
30985   { 12612 /* vpcmpeqw */, X86::VPCMPEQWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
30987   { 12612 /* vpcmpeqw */, X86::VPCMPEQWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
30989   { 12612 /* vpcmpeqw */, X86::VPCMPEQWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
30991   { 12612 /* vpcmpeqw */, X86::VPCMPEQWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
31003   { 12643 /* vpcmpgtb */, X86::VPCMPGTBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
31005   { 12643 /* vpcmpgtb */, X86::VPCMPGTBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
31007   { 12643 /* vpcmpgtb */, X86::VPCMPGTBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
31009   { 12643 /* vpcmpgtb */, X86::VPCMPGTBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
31011   { 12643 /* vpcmpgtb */, X86::VPCMPGTBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
31019   { 12652 /* vpcmpgtd */, X86::VPCMPGTDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
31021   { 12652 /* vpcmpgtd */, X86::VPCMPGTDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
31023   { 12652 /* vpcmpgtd */, X86::VPCMPGTDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
31025   { 12652 /* vpcmpgtd */, X86::VPCMPGTDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
31027   { 12652 /* vpcmpgtd */, X86::VPCMPGTDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
31041   { 12661 /* vpcmpgtq */, X86::VPCMPGTQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
31043   { 12661 /* vpcmpgtq */, X86::VPCMPGTQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
31045   { 12661 /* vpcmpgtq */, X86::VPCMPGTQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
31047   { 12661 /* vpcmpgtq */, X86::VPCMPGTQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
31049   { 12661 /* vpcmpgtq */, X86::VPCMPGTQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
31063   { 12670 /* vpcmpgtw */, X86::VPCMPGTWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
31065   { 12670 /* vpcmpgtw */, X86::VPCMPGTWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
31067   { 12670 /* vpcmpgtw */, X86::VPCMPGTWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
31069   { 12670 /* vpcmpgtw */, X86::VPCMPGTWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
31071   { 12670 /* vpcmpgtw */, X86::VPCMPGTWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
31415   { 12939 /* vpermb */, X86::VPERMBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
31417   { 12939 /* vpermb */, X86::VPERMBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
31419   { 12939 /* vpermb */, X86::VPERMBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
31433   { 12946 /* vpermd */, X86::VPERMDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
31435   { 12946 /* vpermd */, X86::VPERMDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
31437   { 12946 /* vpermd */, X86::VPERMDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
31609   { 13031 /* vpermilpd */, X86::VPERMILPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
31613   { 13031 /* vpermilpd */, X86::VPERMILPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
31617   { 13031 /* vpermilpd */, X86::VPERMILPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
31621   { 13031 /* vpermilpd */, X86::VPERMILPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
31625   { 13031 /* vpermilpd */, X86::VPERMILPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
31671   { 13041 /* vpermilps */, X86::VPERMILPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
31675   { 13041 /* vpermilps */, X86::VPERMILPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
31679   { 13041 /* vpermilps */, X86::VPERMILPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
31683   { 13041 /* vpermilps */, X86::VPERMILPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
31687   { 13041 /* vpermilps */, X86::VPERMILPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
31735   { 13051 /* vpermpd */, X86::VPERMPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
31739   { 13051 /* vpermpd */, X86::VPERMPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
31771   { 13059 /* vpermps */, X86::VPERMPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
31773   { 13059 /* vpermps */, X86::VPERMPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
31775   { 13059 /* vpermps */, X86::VPERMPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
31793   { 13067 /* vpermq */, X86::VPERMQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
31797   { 13067 /* vpermq */, X86::VPERMQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
31973   { 13130 /* vpermw */, X86::VPERMWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
31975   { 13130 /* vpermw */, X86::VPERMWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
31977   { 13130 /* vpermw */, X86::VPERMWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32105   { 13280 /* vphaddd */, X86::VPHADDDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32107   { 13280 /* vphaddd */, X86::VPHADDDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32111   { 13297 /* vphaddsw */, X86::VPHADDSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32113   { 13297 /* vphaddsw */, X86::VPHADDSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32127   { 13366 /* vphaddw */, X86::VPHADDWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32129   { 13366 /* vphaddw */, X86::VPHADDWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32139   { 13413 /* vphsubd */, X86::VPHSUBDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32141   { 13413 /* vphsubd */, X86::VPHSUBDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32145   { 13430 /* vphsubsw */, X86::VPHSUBSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32147   { 13430 /* vphsubsw */, X86::VPHSUBSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32149   { 13439 /* vphsubw */, X86::VPHSUBWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32151   { 13439 /* vphsubw */, X86::VPHSUBWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32303   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32305   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32307   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32309   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32311   { 13650 /* vpmaddubsw */, X86::VPMADDUBSWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32325   { 13661 /* vpmaddwd */, X86::VPMADDWDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32327   { 13661 /* vpmaddwd */, X86::VPMADDWDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32329   { 13661 /* vpmaddwd */, X86::VPMADDWDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32331   { 13661 /* vpmaddwd */, X86::VPMADDWDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32333   { 13661 /* vpmaddwd */, X86::VPMADDWDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32355   { 13692 /* vpmaxsb */, X86::VPMAXSBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32357   { 13692 /* vpmaxsb */, X86::VPMAXSBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32359   { 13692 /* vpmaxsb */, X86::VPMAXSBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32361   { 13692 /* vpmaxsb */, X86::VPMAXSBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32363   { 13692 /* vpmaxsb */, X86::VPMAXSBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32377   { 13700 /* vpmaxsd */, X86::VPMAXSDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32379   { 13700 /* vpmaxsd */, X86::VPMAXSDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32381   { 13700 /* vpmaxsd */, X86::VPMAXSDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32383   { 13700 /* vpmaxsd */, X86::VPMAXSDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32385   { 13700 /* vpmaxsd */, X86::VPMAXSDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32408   { 13708 /* vpmaxsq */, X86::VPMAXSQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32410   { 13708 /* vpmaxsq */, X86::VPMAXSQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32412   { 13708 /* vpmaxsq */, X86::VPMAXSQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32435   { 13716 /* vpmaxsw */, X86::VPMAXSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32437   { 13716 /* vpmaxsw */, X86::VPMAXSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32439   { 13716 /* vpmaxsw */, X86::VPMAXSWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32441   { 13716 /* vpmaxsw */, X86::VPMAXSWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32443   { 13716 /* vpmaxsw */, X86::VPMAXSWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32457   { 13724 /* vpmaxub */, X86::VPMAXUBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32459   { 13724 /* vpmaxub */, X86::VPMAXUBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32461   { 13724 /* vpmaxub */, X86::VPMAXUBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32463   { 13724 /* vpmaxub */, X86::VPMAXUBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32465   { 13724 /* vpmaxub */, X86::VPMAXUBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32479   { 13732 /* vpmaxud */, X86::VPMAXUDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32481   { 13732 /* vpmaxud */, X86::VPMAXUDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32483   { 13732 /* vpmaxud */, X86::VPMAXUDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32485   { 13732 /* vpmaxud */, X86::VPMAXUDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32487   { 13732 /* vpmaxud */, X86::VPMAXUDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32510   { 13740 /* vpmaxuq */, X86::VPMAXUQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32512   { 13740 /* vpmaxuq */, X86::VPMAXUQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32514   { 13740 /* vpmaxuq */, X86::VPMAXUQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32537   { 13748 /* vpmaxuw */, X86::VPMAXUWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32539   { 13748 /* vpmaxuw */, X86::VPMAXUWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32541   { 13748 /* vpmaxuw */, X86::VPMAXUWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32543   { 13748 /* vpmaxuw */, X86::VPMAXUWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32545   { 13748 /* vpmaxuw */, X86::VPMAXUWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32559   { 13756 /* vpminsb */, X86::VPMINSBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32561   { 13756 /* vpminsb */, X86::VPMINSBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32563   { 13756 /* vpminsb */, X86::VPMINSBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32565   { 13756 /* vpminsb */, X86::VPMINSBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32567   { 13756 /* vpminsb */, X86::VPMINSBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32581   { 13764 /* vpminsd */, X86::VPMINSDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32583   { 13764 /* vpminsd */, X86::VPMINSDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32585   { 13764 /* vpminsd */, X86::VPMINSDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32587   { 13764 /* vpminsd */, X86::VPMINSDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32589   { 13764 /* vpminsd */, X86::VPMINSDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32612   { 13772 /* vpminsq */, X86::VPMINSQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32614   { 13772 /* vpminsq */, X86::VPMINSQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32616   { 13772 /* vpminsq */, X86::VPMINSQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32639   { 13780 /* vpminsw */, X86::VPMINSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32641   { 13780 /* vpminsw */, X86::VPMINSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32643   { 13780 /* vpminsw */, X86::VPMINSWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32645   { 13780 /* vpminsw */, X86::VPMINSWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32647   { 13780 /* vpminsw */, X86::VPMINSWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32661   { 13788 /* vpminub */, X86::VPMINUBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32663   { 13788 /* vpminub */, X86::VPMINUBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32665   { 13788 /* vpminub */, X86::VPMINUBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32667   { 13788 /* vpminub */, X86::VPMINUBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32669   { 13788 /* vpminub */, X86::VPMINUBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32683   { 13796 /* vpminud */, X86::VPMINUDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32685   { 13796 /* vpminud */, X86::VPMINUDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32687   { 13796 /* vpminud */, X86::VPMINUDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32689   { 13796 /* vpminud */, X86::VPMINUDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32691   { 13796 /* vpminud */, X86::VPMINUDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32714   { 13804 /* vpminuq */, X86::VPMINUQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32716   { 13804 /* vpminuq */, X86::VPMINUQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32718   { 13804 /* vpminuq */, X86::VPMINUQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
32741   { 13812 /* vpminuw */, X86::VPMINUWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
32743   { 13812 /* vpminuw */, X86::VPMINUWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
32745   { 13812 /* vpminuw */, X86::VPMINUWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
32747   { 13812 /* vpminuw */, X86::VPMINUWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
32749   { 13812 /* vpminuw */, X86::VPMINUWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33323   { 14184 /* vpmuldq */, X86::VPMULDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33325   { 14184 /* vpmuldq */, X86::VPMULDQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
33327   { 14184 /* vpmuldq */, X86::VPMULDQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33329   { 14184 /* vpmuldq */, X86::VPMULDQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33331   { 14184 /* vpmuldq */, X86::VPMULDQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33354   { 14192 /* vpmulhrsw */, X86::VPMULHRSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33356   { 14192 /* vpmulhrsw */, X86::VPMULHRSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
33358   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33360   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33362   { 14192 /* vpmulhrsw */, X86::VPMULHRSWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33376   { 14202 /* vpmulhuw */, X86::VPMULHUWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33378   { 14202 /* vpmulhuw */, X86::VPMULHUWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
33380   { 14202 /* vpmulhuw */, X86::VPMULHUWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33382   { 14202 /* vpmulhuw */, X86::VPMULHUWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33384   { 14202 /* vpmulhuw */, X86::VPMULHUWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33398   { 14211 /* vpmulhw */, X86::VPMULHWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33400   { 14211 /* vpmulhw */, X86::VPMULHWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
33402   { 14211 /* vpmulhw */, X86::VPMULHWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33404   { 14211 /* vpmulhw */, X86::VPMULHWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33406   { 14211 /* vpmulhw */, X86::VPMULHWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33420   { 14219 /* vpmulld */, X86::VPMULLDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33422   { 14219 /* vpmulld */, X86::VPMULLDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
33424   { 14219 /* vpmulld */, X86::VPMULLDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33426   { 14219 /* vpmulld */, X86::VPMULLDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33428   { 14219 /* vpmulld */, X86::VPMULLDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33451   { 14227 /* vpmullq */, X86::VPMULLQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33453   { 14227 /* vpmullq */, X86::VPMULLQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33455   { 14227 /* vpmullq */, X86::VPMULLQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33478   { 14235 /* vpmullw */, X86::VPMULLWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33480   { 14235 /* vpmullw */, X86::VPMULLWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
33482   { 14235 /* vpmullw */, X86::VPMULLWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33484   { 14235 /* vpmullw */, X86::VPMULLWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33486   { 14235 /* vpmullw */, X86::VPMULLWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33500   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33502   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33504   { 14243 /* vpmultishiftqb */, X86::VPMULTISHIFTQBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33527   { 14258 /* vpmuludq */, X86::VPMULUDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33529   { 14258 /* vpmuludq */, X86::VPMULUDQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
33531   { 14258 /* vpmuludq */, X86::VPMULUDQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33533   { 14258 /* vpmuludq */, X86::VPMULUDQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33535   { 14258 /* vpmuludq */, X86::VPMULUDQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33648   { 14303 /* vpor */, X86::VPORrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33650   { 14303 /* vpor */, X86::VPORYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
33652   { 14308 /* vpord */, X86::VPORDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33654   { 14308 /* vpord */, X86::VPORDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33656   { 14308 /* vpord */, X86::VPORDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33679   { 14314 /* vporq */, X86::VPORQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33681   { 14314 /* vporq */, X86::VPORQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33683   { 14314 /* vporq */, X86::VPORQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33763   { 14341 /* vprolvd */, X86::VPROLVDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33765   { 14341 /* vprolvd */, X86::VPROLVDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33767   { 14341 /* vprolvd */, X86::VPROLVDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33790   { 14349 /* vprolvq */, X86::VPROLVQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33792   { 14349 /* vprolvq */, X86::VPROLVQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33794   { 14349 /* vprolvq */, X86::VPROLVQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33871   { 14371 /* vprorvd */, X86::VPRORVDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33873   { 14371 /* vprorvd */, X86::VPRORVDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33875   { 14371 /* vprorvd */, X86::VPRORVDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33898   { 14379 /* vprorvq */, X86::VPRORVQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33900   { 14379 /* vprorvq */, X86::VPRORVQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33902   { 14379 /* vprorvq */, X86::VPRORVQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33925   { 14387 /* vprotb */, X86::VPROTBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33930   { 14394 /* vprotd */, X86::VPROTDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33935   { 14401 /* vprotq */, X86::VPROTQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33940   { 14408 /* vprotw */, X86::VPROTWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33945   { 14415 /* vpsadbw */, X86::VPSADBWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33947   { 14415 /* vpsadbw */, X86::VPSADBWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
33949   { 14415 /* vpsadbw */, X86::VPSADBWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
33951   { 14415 /* vpsadbw */, X86::VPSADBWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
33953   { 14415 /* vpsadbw */, X86::VPSADBWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
33967   { 14471 /* vpshab */, X86::VPSHABrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33970   { 14478 /* vpshad */, X86::VPSHADrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33973   { 14485 /* vpshaq */, X86::VPSHAQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33976   { 14492 /* vpshaw */, X86::VPSHAWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33979   { 14499 /* vpshlb */, X86::VPSHLBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
33982   { 14506 /* vpshld */, X86::VPSHLDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34129   { 14564 /* vpshlq */, X86::VPSHLQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34132   { 14571 /* vpshlw */, X86::VPSHLWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34279   { 14629 /* vpshufb */, X86::VPSHUFBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34281   { 14629 /* vpshufb */, X86::VPSHUFBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
34283   { 14629 /* vpshufb */, X86::VPSHUFBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34285   { 14629 /* vpshufb */, X86::VPSHUFBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
34287   { 14629 /* vpshufb */, X86::VPSHUFBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
34301   { 14637 /* vpshufbitqmb */, X86::VPSHUFBITQMBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
34303   { 14637 /* vpshufbitqmb */, X86::VPSHUFBITQMBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
34305   { 14637 /* vpshufbitqmb */, X86::VPSHUFBITQMBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
34388   { 14676 /* vpsignb */, X86::VPSIGNBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34390   { 14676 /* vpsignb */, X86::VPSIGNBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
34392   { 14684 /* vpsignd */, X86::VPSIGNDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34394   { 14684 /* vpsignd */, X86::VPSIGNDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
34396   { 14692 /* vpsignw */, X86::VPSIGNWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34398   { 14692 /* vpsignw */, X86::VPSIGNWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
34400   { 14700 /* vpslld */, X86::VPSLLDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34403   { 14700 /* vpslld */, X86::VPSLLDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_FR32 }, },
34406   { 14700 /* vpslld */, X86::VPSLLDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34410   { 14700 /* vpslld */, X86::VPSLLDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_FR32X }, },
34414   { 14700 /* vpslld */, X86::VPSLLDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_FR32X }, },
34459   { 14715 /* vpsllq */, X86::VPSLLQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34462   { 14715 /* vpsllq */, X86::VPSLLQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_FR32 }, },
34465   { 14715 /* vpsllq */, X86::VPSLLQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34469   { 14715 /* vpsllq */, X86::VPSLLQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_FR32X }, },
34473   { 14715 /* vpsllq */, X86::VPSLLQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_FR32X }, },
34510   { 14722 /* vpsllvd */, X86::VPSLLVDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34512   { 14722 /* vpsllvd */, X86::VPSLLVDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
34514   { 14722 /* vpsllvd */, X86::VPSLLVDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34516   { 14722 /* vpsllvd */, X86::VPSLLVDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
34518   { 14722 /* vpsllvd */, X86::VPSLLVDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
34541   { 14730 /* vpsllvq */, X86::VPSLLVQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34543   { 14730 /* vpsllvq */, X86::VPSLLVQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
34545   { 14730 /* vpsllvq */, X86::VPSLLVQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34547   { 14730 /* vpsllvq */, X86::VPSLLVQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
34549   { 14730 /* vpsllvq */, X86::VPSLLVQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
34572   { 14738 /* vpsllvw */, X86::VPSLLVWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34574   { 14738 /* vpsllvw */, X86::VPSLLVWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
34576   { 14738 /* vpsllvw */, X86::VPSLLVWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
34590   { 14746 /* vpsllw */, X86::VPSLLWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34593   { 14746 /* vpsllw */, X86::VPSLLWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_FR32 }, },
34596   { 14746 /* vpsllw */, X86::VPSLLWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34600   { 14746 /* vpsllw */, X86::VPSLLWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_FR32X }, },
34604   { 14746 /* vpsllw */, X86::VPSLLWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_FR32X }, },
34632   { 14753 /* vpsrad */, X86::VPSRADrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34635   { 14753 /* vpsrad */, X86::VPSRADYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_FR32 }, },
34638   { 14753 /* vpsrad */, X86::VPSRADZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34642   { 14753 /* vpsrad */, X86::VPSRADZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_FR32X }, },
34646   { 14753 /* vpsrad */, X86::VPSRADZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_FR32X }, },
34683   { 14760 /* vpsraq */, X86::VPSRAQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34687   { 14760 /* vpsraq */, X86::VPSRAQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_FR32X }, },
34691   { 14760 /* vpsraq */, X86::VPSRAQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_FR32X }, },
34728   { 14767 /* vpsravd */, X86::VPSRAVDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34730   { 14767 /* vpsravd */, X86::VPSRAVDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
34732   { 14767 /* vpsravd */, X86::VPSRAVDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34734   { 14767 /* vpsravd */, X86::VPSRAVDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
34736   { 14767 /* vpsravd */, X86::VPSRAVDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
34759   { 14775 /* vpsravq */, X86::VPSRAVQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34761   { 14775 /* vpsravq */, X86::VPSRAVQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
34763   { 14775 /* vpsravq */, X86::VPSRAVQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
34786   { 14783 /* vpsravw */, X86::VPSRAVWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34788   { 14783 /* vpsravw */, X86::VPSRAVWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
34790   { 14783 /* vpsravw */, X86::VPSRAVWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
34804   { 14791 /* vpsraw */, X86::VPSRAWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34807   { 14791 /* vpsraw */, X86::VPSRAWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_FR32 }, },
34810   { 14791 /* vpsraw */, X86::VPSRAWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34814   { 14791 /* vpsraw */, X86::VPSRAWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_FR32X }, },
34818   { 14791 /* vpsraw */, X86::VPSRAWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_FR32X }, },
34846   { 14798 /* vpsrld */, X86::VPSRLDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34849   { 14798 /* vpsrld */, X86::VPSRLDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_FR32 }, },
34852   { 14798 /* vpsrld */, X86::VPSRLDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34856   { 14798 /* vpsrld */, X86::VPSRLDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_FR32X }, },
34860   { 14798 /* vpsrld */, X86::VPSRLDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_FR32X }, },
34905   { 14813 /* vpsrlq */, X86::VPSRLQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34908   { 14813 /* vpsrlq */, X86::VPSRLQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_FR32 }, },
34911   { 14813 /* vpsrlq */, X86::VPSRLQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34915   { 14813 /* vpsrlq */, X86::VPSRLQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_FR32X }, },
34919   { 14813 /* vpsrlq */, X86::VPSRLQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_FR32X }, },
34956   { 14820 /* vpsrlvd */, X86::VPSRLVDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34958   { 14820 /* vpsrlvd */, X86::VPSRLVDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
34960   { 14820 /* vpsrlvd */, X86::VPSRLVDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34962   { 14820 /* vpsrlvd */, X86::VPSRLVDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
34964   { 14820 /* vpsrlvd */, X86::VPSRLVDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
34987   { 14828 /* vpsrlvq */, X86::VPSRLVQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
34989   { 14828 /* vpsrlvq */, X86::VPSRLVQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
34991   { 14828 /* vpsrlvq */, X86::VPSRLVQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
34993   { 14828 /* vpsrlvq */, X86::VPSRLVQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
34995   { 14828 /* vpsrlvq */, X86::VPSRLVQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35018   { 14836 /* vpsrlvw */, X86::VPSRLVWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35020   { 14836 /* vpsrlvw */, X86::VPSRLVWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35022   { 14836 /* vpsrlvw */, X86::VPSRLVWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35036   { 14844 /* vpsrlw */, X86::VPSRLWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35039   { 14844 /* vpsrlw */, X86::VPSRLWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_FR32 }, },
35042   { 14844 /* vpsrlw */, X86::VPSRLWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35046   { 14844 /* vpsrlw */, X86::VPSRLWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_FR32X }, },
35050   { 14844 /* vpsrlw */, X86::VPSRLWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_FR32X }, },
35078   { 14851 /* vpsubb */, X86::VPSUBBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35080   { 14851 /* vpsubb */, X86::VPSUBBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35082   { 14851 /* vpsubb */, X86::VPSUBBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35084   { 14851 /* vpsubb */, X86::VPSUBBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35086   { 14851 /* vpsubb */, X86::VPSUBBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35100   { 14858 /* vpsubd */, X86::VPSUBDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35102   { 14858 /* vpsubd */, X86::VPSUBDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35104   { 14858 /* vpsubd */, X86::VPSUBDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35106   { 14858 /* vpsubd */, X86::VPSUBDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35108   { 14858 /* vpsubd */, X86::VPSUBDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35131   { 14865 /* vpsubq */, X86::VPSUBQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35133   { 14865 /* vpsubq */, X86::VPSUBQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35135   { 14865 /* vpsubq */, X86::VPSUBQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35137   { 14865 /* vpsubq */, X86::VPSUBQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35139   { 14865 /* vpsubq */, X86::VPSUBQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35162   { 14872 /* vpsubsb */, X86::VPSUBSBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35164   { 14872 /* vpsubsb */, X86::VPSUBSBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35166   { 14872 /* vpsubsb */, X86::VPSUBSBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35168   { 14872 /* vpsubsb */, X86::VPSUBSBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35170   { 14872 /* vpsubsb */, X86::VPSUBSBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35184   { 14880 /* vpsubsw */, X86::VPSUBSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35186   { 14880 /* vpsubsw */, X86::VPSUBSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35188   { 14880 /* vpsubsw */, X86::VPSUBSWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35190   { 14880 /* vpsubsw */, X86::VPSUBSWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35192   { 14880 /* vpsubsw */, X86::VPSUBSWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35206   { 14888 /* vpsubusb */, X86::VPSUBUSBrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35208   { 14888 /* vpsubusb */, X86::VPSUBUSBYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35210   { 14888 /* vpsubusb */, X86::VPSUBUSBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35212   { 14888 /* vpsubusb */, X86::VPSUBUSBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35214   { 14888 /* vpsubusb */, X86::VPSUBUSBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35228   { 14897 /* vpsubusw */, X86::VPSUBUSWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35230   { 14897 /* vpsubusw */, X86::VPSUBUSWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35232   { 14897 /* vpsubusw */, X86::VPSUBUSWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35234   { 14897 /* vpsubusw */, X86::VPSUBUSWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35236   { 14897 /* vpsubusw */, X86::VPSUBUSWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35250   { 14906 /* vpsubw */, X86::VPSUBWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35252   { 14906 /* vpsubw */, X86::VPSUBWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35254   { 14906 /* vpsubw */, X86::VPSUBWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35256   { 14906 /* vpsubw */, X86::VPSUBWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35258   { 14906 /* vpsubw */, X86::VPSUBWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35330   { 14942 /* vptestmb */, X86::VPTESTMBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
35332   { 14942 /* vptestmb */, X86::VPTESTMBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
35334   { 14942 /* vptestmb */, X86::VPTESTMBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
35342   { 14951 /* vptestmd */, X86::VPTESTMDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
35344   { 14951 /* vptestmd */, X86::VPTESTMDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
35346   { 14951 /* vptestmd */, X86::VPTESTMDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
35360   { 14960 /* vptestmq */, X86::VPTESTMQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
35362   { 14960 /* vptestmq */, X86::VPTESTMQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
35364   { 14960 /* vptestmq */, X86::VPTESTMQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
35378   { 14969 /* vptestmw */, X86::VPTESTMWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
35380   { 14969 /* vptestmw */, X86::VPTESTMWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
35382   { 14969 /* vptestmw */, X86::VPTESTMWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
35390   { 14978 /* vptestnmb */, X86::VPTESTNMBZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
35392   { 14978 /* vptestnmb */, X86::VPTESTNMBZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
35394   { 14978 /* vptestnmb */, X86::VPTESTNMBZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
35402   { 14988 /* vptestnmd */, X86::VPTESTNMDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
35404   { 14988 /* vptestnmd */, X86::VPTESTNMDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
35406   { 14988 /* vptestnmd */, X86::VPTESTNMDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
35420   { 14998 /* vptestnmq */, X86::VPTESTNMQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
35422   { 14998 /* vptestnmq */, X86::VPTESTNMQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
35424   { 14998 /* vptestnmq */, X86::VPTESTNMQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
35438   { 15008 /* vptestnmw */, X86::VPTESTNMWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_FR32X, MCK_FR32X }, },
35440   { 15008 /* vptestnmw */, X86::VPTESTNMWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR256X, MCK_VR256X }, },
35442   { 15008 /* vptestnmw */, X86::VPTESTNMWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VK1, MCK_VR512, MCK_VR512 }, },
35450   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35452   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35454   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35456   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35458   { 15018 /* vpunpckhbw */, X86::VPUNPCKHBWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35472   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35474   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35476   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35478   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35480   { 15029 /* vpunpckhdq */, X86::VPUNPCKHDQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35503   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35505   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35507   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35509   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35511   { 15040 /* vpunpckhqdq */, X86::VPUNPCKHQDQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35534   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35536   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35538   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35540   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35542   { 15052 /* vpunpckhwd */, X86::VPUNPCKHWDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35556   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35558   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35560   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35562   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35564   { 15063 /* vpunpcklbw */, X86::VPUNPCKLBWZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35578   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35580   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35582   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35584   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35586   { 15074 /* vpunpckldq */, X86::VPUNPCKLDQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35609   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35611   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35613   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35615   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35617   { 15085 /* vpunpcklqdq */, X86::VPUNPCKLQDQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35640   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35642   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35644   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35646   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35648   { 15097 /* vpunpcklwd */, X86::VPUNPCKLWDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35662   { 15108 /* vpxor */, X86::VPXORrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
35664   { 15108 /* vpxor */, X86::VPXORYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
35666   { 15114 /* vpxord */, X86::VPXORDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35668   { 15114 /* vpxord */, X86::VPXORDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35670   { 15114 /* vpxord */, X86::VPXORDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35693   { 15121 /* vpxorq */, X86::VPXORQZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35695   { 15121 /* vpxorq */, X86::VPXORQZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
35697   { 15121 /* vpxorq */, X86::VPXORQZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
35852   { 15182 /* vrcp14sd */, X86::VRCP14SDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35858   { 15191 /* vrcp14ss */, X86::VRCP14SSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35888   { 15218 /* vrcp28sd */, X86::VRCP28SDZr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35890   { 15218 /* vrcp28sd */, X86::VRCP28SDZrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
35897   { 15227 /* vrcp28ss */, X86::VRCP28SSZr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
35899   { 15227 /* vrcp28ss */, X86::VRCP28SSZrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
35910   { 15243 /* vrcpss */, X86::VRCPSSr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36134   { 15396 /* vrsqrt14sd */, X86::VRSQRT14SDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36140   { 15407 /* vrsqrt14ss */, X86::VRSQRT14SSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36170   { 15440 /* vrsqrt28sd */, X86::VRSQRT28SDZr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36172   { 15440 /* vrsqrt28sd */, X86::VRSQRT28SDZrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
36179   { 15451 /* vrsqrt28ss */, X86::VRSQRT28SSZr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36181   { 15451 /* vrsqrt28ss */, X86::VRSQRT28SSZrb, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X, MCK__123_sae_125_ }, },
36192   { 15471 /* vrsqrtss */, X86::VRSQRTSSr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36194   { 15480 /* vscalefpd */, X86::VSCALEFPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36196   { 15480 /* vscalefpd */, X86::VSCALEFPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36198   { 15480 /* vscalefpd */, X86::VSCALEFPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
36224   { 15490 /* vscalefps */, X86::VSCALEFPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36226   { 15490 /* vscalefps */, X86::VSCALEFPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36228   { 15490 /* vscalefps */, X86::VSCALEFPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
36254   { 15500 /* vscalefsd */, X86::VSCALEFSDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36263   { 15510 /* vscalefss */, X86::VSCALEFSSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36494   { 15764 /* vsqrtsd */, X86::VSQRTSDr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36496   { 15764 /* vsqrtsd */, X86::VSQRTSDZr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36505   { 15772 /* vsqrtss */, X86::VSQRTSSr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36507   { 15772 /* vsqrtss */, X86::VSQRTSSZr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36517   { 15789 /* vsubpd */, X86::VSUBPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36519   { 15789 /* vsubpd */, X86::VSUBPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
36521   { 15789 /* vsubpd */, X86::VSUBPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36523   { 15789 /* vsubpd */, X86::VSUBPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36525   { 15789 /* vsubpd */, X86::VSUBPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
36551   { 15796 /* vsubps */, X86::VSUBPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36553   { 15796 /* vsubps */, X86::VSUBPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
36555   { 15796 /* vsubps */, X86::VSUBPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36557   { 15796 /* vsubps */, X86::VSUBPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36559   { 15796 /* vsubps */, X86::VSUBPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
36585   { 15803 /* vsubsd */, X86::VSUBSDrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36587   { 15803 /* vsubsd */, X86::VSUBSDZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36596   { 15810 /* vsubss */, X86::VSUBSSrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36598   { 15810 /* vsubss */, X86::VSUBSSZrr_Int, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36625   { 15851 /* vunpckhpd */, X86::VUNPCKHPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36627   { 15851 /* vunpckhpd */, X86::VUNPCKHPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
36629   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36631   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36633   { 15851 /* vunpckhpd */, X86::VUNPCKHPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
36656   { 15861 /* vunpckhps */, X86::VUNPCKHPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36658   { 15861 /* vunpckhps */, X86::VUNPCKHPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
36660   { 15861 /* vunpckhps */, X86::VUNPCKHPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36662   { 15861 /* vunpckhps */, X86::VUNPCKHPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36664   { 15861 /* vunpckhps */, X86::VUNPCKHPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
36687   { 15871 /* vunpcklpd */, X86::VUNPCKLPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36689   { 15871 /* vunpcklpd */, X86::VUNPCKLPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
36691   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36693   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36695   { 15871 /* vunpcklpd */, X86::VUNPCKLPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
36718   { 15881 /* vunpcklps */, X86::VUNPCKLPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36720   { 15881 /* vunpcklps */, X86::VUNPCKLPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
36722   { 15881 /* vunpcklps */, X86::VUNPCKLPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36724   { 15881 /* vunpcklps */, X86::VUNPCKLPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36726   { 15881 /* vunpcklps */, X86::VUNPCKLPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
36749   { 15891 /* vxorpd */, X86::VXORPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36751   { 15891 /* vxorpd */, X86::VXORPDYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
36753   { 15891 /* vxorpd */, X86::VXORPDZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36755   { 15891 /* vxorpd */, X86::VXORPDZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36757   { 15891 /* vxorpd */, X86::VXORPDZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },
36780   { 15898 /* vxorps */, X86::VXORPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32, MCK_FR32, MCK_FR32 }, },
36782   { 15898 /* vxorps */, X86::VXORPSYrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256, MCK_VR256, MCK_VR256 }, },
36784   { 15898 /* vxorps */, X86::VXORPSZ128rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_FR32X, MCK_FR32X, MCK_FR32X }, },
36786   { 15898 /* vxorps */, X86::VXORPSZ256rr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR256X, MCK_VR256X, MCK_VR256X }, },
36788   { 15898 /* vxorps */, X86::VXORPSZrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VR512, MCK_VR512, MCK_VR512 }, },