reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1995 { 440, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #440 = CALL_INDIRECT_VOID 1996 { 441, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #441 = CALL_INDIRECT_VOID_S 1998 { 443, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #443 = CALL_INDIRECT_exnref_S 2000 { 445, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #445 = CALL_INDIRECT_f32_S 2002 { 447, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #447 = CALL_INDIRECT_f64_S 2004 { 449, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #449 = CALL_INDIRECT_i32_S 2006 { 451, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #451 = CALL_INDIRECT_i64_S 2008 { 453, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #453 = CALL_INDIRECT_v16i8_S 2010 { 455, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #455 = CALL_INDIRECT_v2f64_S 2012 { 457, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #457 = CALL_INDIRECT_v2i64_S 2014 { 459, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #459 = CALL_INDIRECT_v4f32_S 2016 { 461, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #461 = CALL_INDIRECT_v4i32_S 2018 { 463, 2, 0, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #463 = CALL_INDIRECT_v8i16_S 2676 { 1121, 2, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #1121 = RET_CALL_INDIRECT 2677 { 1122, 2, 0, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #1122 = RET_CALL_INDIRECT_S