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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 5299 { 979, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #979 = CLRBAsmE
5300 { 980, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #980 = CLRBAsmH
5301 { 981, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #981 = CLRBAsmHE
5302 { 982, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #982 = CLRBAsmL
5303 { 983, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #983 = CLRBAsmLE
5304 { 984, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #984 = CLRBAsmLH
5305 { 985, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #985 = CLRBAsmNE
5306 { 986, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #986 = CLRBAsmNH
5307 { 987, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #987 = CLRBAsmNHE
5308 { 988, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #988 = CLRBAsmNL
5309 { 989, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #989 = CLRBAsmNLE
5310 { 990, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #990 = CLRBAsmNLH
5368 { 1048, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1048 = CRBAsmE
5369 { 1049, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1049 = CRBAsmH
5370 { 1050, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1050 = CRBAsmHE
5371 { 1051, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1051 = CRBAsmL
5372 { 1052, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1052 = CRBAsmLE
5373 { 1053, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1053 = CRBAsmLH
5374 { 1054, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1054 = CRBAsmNE
5375 { 1055, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1055 = CRBAsmNH
5376 { 1056, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1056 = CRBAsmNHE
5377 { 1057, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1057 = CRBAsmNL
5378 { 1058, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1058 = CRBAsmNLE
5379 { 1059, 4, 0, 6, 12, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1059 = CRBAsmNLH
5478 { 1158, 4, 0, 4, 819, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1158 = DIAG
5647 { 1327, 4, 1, 6, 268, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo183, -1 ,nullptr }, // Inst #1327 = LAA
5649 { 1329, 4, 1, 6, 269, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo183, -1 ,nullptr }, // Inst #1329 = LAAL
5655 { 1335, 4, 1, 6, 270, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo183, -1 ,nullptr }, // Inst #1335 = LAN
5657 { 1337, 4, 1, 6, 271, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo183, -1 ,nullptr }, // Inst #1337 = LAO
5662 { 1342, 4, 1, 6, 272, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo183, -1 ,nullptr }, // Inst #1342 = LAX
5762 { 1442, 4, 2, 4, 79, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1442 = LM
5766 { 1446, 4, 2, 6, 79, 0|(1ULL<<MCID::MayLoad), 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1446 = LMY
6444 { 2124, 4, 0, 4, 81, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2124 = STM
6447 { 2127, 4, 0, 6, 81, 0|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2127 = STMY
6569 { 2249, 4, 0, 4, 820, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2249 = TRACE