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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Sparc/SparcGenAsmMatcher.inc 2085 case SP::O0: OpKind = MCK_IntRegs; break;
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 1078 { SP::O0 },
1131 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1151 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1260 { 8U, SP::O0 },
1345 { 8U, SP::O0 },
1495 { SP::O0, 8U },
1580 { SP::O0, 8U },
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 131 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
412 else if (Reg >= Sparc::O0 && Reg <= Sparc::O7)
413 regIdx = Reg - Sparc::O0 + 8;
lib/Target/Sparc/DelaySlotFiller.cpp 396 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
435 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
469 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 64 SP::O0, SP::O1, SP::O2, SP::O3,
lib/Target/Sparc/SparcFrameLowering.cpp 339 unsigned mapped_reg = reg - SP::I0 + SP::O0;
365 MBB->addLiveIn(reg - SP::I0 + SP::O0);
lib/Target/Sparc/SparcISelLowering.cpp 189 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
192 return Reg - SP::I0 + SP::O0;
1024 .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3)
2051 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
2063 DAG.getRegister(SP::O0, PtrVT),
2071 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);