reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Sparc/SparcGenAsmMatcher.inc

 2108     case SP::I7: OpKind = MCK_IntRegs; break;

gen/lib/Target/Sparc/SparcGenRegisterInfo.inc

 1069   { SP::I7 },
 1131     SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7, 
 1151     SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7, 
 1283   { 31U, SP::I7 },
 1368   { 31U, SP::I7 },
 1486   { SP::I7, 31U },
 1571   { SP::I7, 31U },

lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

  136     Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
  416     else if (Reg >= Sparc::I0 && Reg <= Sparc::I7)

lib/Target/Sparc/DelaySlotFiller.cpp

  384   if (reg < SP::I0 || reg > SP::I7)
  412   if (reg < SP::I0 || reg > SP::I7)
  450   if (reg < SP::I0 || reg > SP::I7)

lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

   69   SP::I4,  SP::I5,  SP::I6,  SP::I7 };

lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp

   71         case SP::I7: O << "\tret"; return true;

lib/Target/Sparc/SparcFrameLowering.cpp

  171   unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
  309   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
  335   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
  361     for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {

lib/Target/Sparc/SparcISelLowering.cpp

  189   static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
  191   if (Reg >= SP::I0 && Reg <= SP::I7)
 1023     .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
 2673     unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));

lib/Target/Sparc/SparcRegisterInfo.cpp

   72   Reserved.set(SP::I7);