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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Sparc/SparcGenAsmMatcher.inc 2101 case SP::I0: OpKind = MCK_IntRegs; break;
gen/lib/Target/Sparc/SparcGenCallingConv.inc 35 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
96 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 1062 { SP::I0 },
1131 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1151 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1276 { 24U, SP::I0 },
1361 { 24U, SP::I0 },
1479 { SP::I0, 24U },
1564 { SP::I0, 24U },
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 135 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
416 else if (Reg >= Sparc::I0 && Reg <= Sparc::I7)
417 regIdx = Reg - Sparc::I0 + 24;
lib/Target/Sparc/DelaySlotFiller.cpp 384 if (reg < SP::I0 || reg > SP::I7)
396 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
412 if (reg < SP::I0 || reg > SP::I7)
435 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
450 if (reg < SP::I0 || reg > SP::I7)
469 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 68 SP::I0, SP::I1, SP::I2, SP::I3,
lib/Target/Sparc/SparcFrameLowering.cpp 309 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
335 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
339 unsigned mapped_reg = reg - SP::I0 + SP::O0;
345 if ((reg - SP::I0) % 2 == 0) {
346 unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
361 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
365 MBB->addLiveIn(reg - SP::I0 + SP::O0);
lib/Target/Sparc/SparcISelLowering.cpp 59 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
87 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
121 Reg = SP::I0 + Offset/8;
166 unsigned Reg = SP::I0 + Offset/8;
189 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
191 if (Reg >= SP::I0 && Reg <= SP::I7)
192 return Reg - SP::I0 + SP::O0;
274 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
276 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
537 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
671 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
1022 .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
1070 unsigned IReg = SP::I0 + Offset/8;
1169 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
lib/Target/Sparc/SparcISelLowering.h 108 return SP::I0;