reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/Sparc/SparcGenAsmMatcher.inc

 2078     case SP::G1: OpKind = MCK_IntRegs; break;

gen/lib/Target/Sparc/SparcGenRegisterInfo.inc

 1055   { SP::G1 },
 1131     SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7, 
 1151     SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7, 
 1253   { 1U, SP::G1 },
 1338   { 1U, SP::G1 },
 1472   { SP::G1, 1U },
 1557   { SP::G1, 1U },

lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

  129     Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,

lib/Target/Sparc/Disassembler/SparcDisassembler.cpp

   62   SP::G0,  SP::G1,  SP::G2,  SP::G3,

lib/Target/Sparc/SparcFrameLowering.cpp

   64     BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
   66     BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
   67       .addReg(SP::G1).addImm(LO10(NumBytes));
   69       .addReg(SP::O6).addReg(SP::G1);
   77   BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
   79   BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
   80     .addReg(SP::G1).addImm(LOX10(NumBytes));
   82     .addReg(SP::O6).addReg(SP::G1);
  184       regUnbiased = SP::G1;

lib/Target/Sparc/SparcISelLowering.cpp

 1028     .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)

lib/Target/Sparc/SparcRegisterInfo.cpp

   58   Reserved.set(SP::G1);
  132     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
  137     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
  137     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
  140     MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
  150   BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
  152   BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
  153     .addReg(SP::G1).addImm(LOX10(Offset));
  155   BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
  155   BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
  158   MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);