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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Sparc/SparcGenInstrInfo.inc 1117 { 187, 3, 1, 4, 1, 0, 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #187 = ADDCCrr
1119 { 189, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #189 = ADDCrr
1121 { 191, 3, 1, 4, 1, 0, 0x0ULL, ImplicitList4, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #191 = ADDErr
1127 { 197, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #197 = ADDrr
1131 { 201, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #201 = ANDCCrr
1133 { 203, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #203 = ANDNCCrr
1135 { 205, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #205 = ANDNrr
1140 { 210, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #210 = ANDrr
1452 { 522, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, ImplicitList7, OperandInfo42, -1 ,nullptr }, // Inst #522 = MULSCCrr
1457 { 527, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #527 = ORCCrr
1459 { 529, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #529 = ORNCCrr
1461 { 531, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #531 = ORNrr
1466 { 536, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #536 = ORrr
1478 { 548, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #548 = RESTORErr
1484 { 554, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #554 = SAVErr
1486 { 556, 3, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList11, ImplicitList7, OperandInfo42, -1 ,nullptr }, // Inst #556 = SDIVCCrr
1490 { 560, 3, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList11, ImplicitList11, OperandInfo42, -1 ,nullptr }, // Inst #560 = SDIVrr
1498 { 568, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #568 = SLLrr
1502 { 572, 3, 1, 4, 18, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo42, -1 ,nullptr }, // Inst #572 = SMULCCrr
1504 { 574, 3, 1, 4, 18, 0, 0x0ULL, nullptr, ImplicitList11, OperandInfo42, -1 ,nullptr }, // Inst #574 = SMULrr
1508 { 578, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #578 = SRArr
1512 { 582, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #582 = SRLrr
1552 { 622, 3, 1, 4, 1, 0, 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #622 = SUBCCrr
1554 { 624, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #624 = SUBCrr
1556 { 626, 3, 1, 4, 1, 0, 0x0ULL, ImplicitList4, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #626 = SUBErr
1560 { 630, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #630 = SUBrr
1568 { 638, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #638 = TADDCCTVrr
1570 { 640, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #640 = TADDCCrr
1581 { 651, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #651 = TSUBCCTVrr
1583 { 653, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #653 = TSUBCCrr
1587 { 657, 3, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList11, ImplicitList7, OperandInfo42, -1 ,nullptr }, // Inst #657 = UDIVCCrr
1591 { 661, 3, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList11, ImplicitList11, OperandInfo42, -1 ,nullptr }, // Inst #661 = UDIVrr
1595 { 665, 3, 1, 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo42, -1 ,nullptr }, // Inst #665 = UMULCCrr
1598 { 668, 3, 1, 4, 21, 0, 0x0ULL, nullptr, ImplicitList11, OperandInfo42, -1 ,nullptr }, // Inst #668 = UMULrr
1624 { 694, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #694 = XNORCCrr
1627 { 697, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #697 = XNORrr
1629 { 699, 3, 1, 4, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #699 = XORCCrr
1633 { 703, 3, 1, 4, 1, 0, 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #703 = XORrr