|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Sparc/SparcGenDisassemblerTables.inc 1789 tmp = fieldFromInstruction(insn, 0, 22);
1790 MI.addOperand(MCOperand::createImm(tmp));
1793 tmp = fieldFromInstruction(insn, 0, 19);
1794 MI.addOperand(MCOperand::createImm(tmp));
1795 tmp = fieldFromInstruction(insn, 25, 4);
1796 MI.addOperand(MCOperand::createImm(tmp));
1799 tmp = fieldFromInstruction(insn, 0, 22);
1800 MI.addOperand(MCOperand::createImm(tmp));
1801 tmp = fieldFromInstruction(insn, 25, 4);
1802 MI.addOperand(MCOperand::createImm(tmp));
1805 tmp = fieldFromInstruction(insn, 14, 5);
1806 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1807 tmp = 0x0;
1808 tmp |= fieldFromInstruction(insn, 0, 14) << 0;
1809 tmp |= fieldFromInstruction(insn, 20, 2) << 14;
1810 MI.addOperand(MCOperand::createImm(tmp));
1815 tmp = fieldFromInstruction(insn, 25, 5);
1816 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1817 tmp = fieldFromInstruction(insn, 0, 22);
1818 MI.addOperand(MCOperand::createImm(tmp));
1821 tmp = fieldFromInstruction(insn, 0, 19);
1822 MI.addOperand(MCOperand::createImm(tmp));
1823 tmp = fieldFromInstruction(insn, 25, 4);
1824 MI.addOperand(MCOperand::createImm(tmp));
1825 tmp = fieldFromInstruction(insn, 20, 2);
1826 if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1829 tmp = fieldFromInstruction(insn, 0, 30);
1830 if (DecodeCall(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1833 tmp = fieldFromInstruction(insn, 25, 5);
1834 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1835 tmp = fieldFromInstruction(insn, 14, 5);
1836 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1837 tmp = fieldFromInstruction(insn, 0, 5);
1838 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1841 tmp = fieldFromInstruction(insn, 25, 5);
1842 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1843 tmp = fieldFromInstruction(insn, 14, 5);
1844 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1845 tmp = fieldFromInstruction(insn, 0, 13);
1846 if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1849 tmp = fieldFromInstruction(insn, 25, 5);
1850 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1851 tmp = fieldFromInstruction(insn, 14, 5);
1852 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1853 tmp = fieldFromInstruction(insn, 0, 5);
1854 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1857 tmp = fieldFromInstruction(insn, 25, 5);
1858 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1859 tmp = fieldFromInstruction(insn, 14, 5);
1860 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1861 tmp = fieldFromInstruction(insn, 0, 13);
1862 MI.addOperand(MCOperand::createImm(tmp));
1865 tmp = fieldFromInstruction(insn, 14, 5);
1866 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1867 tmp = fieldFromInstruction(insn, 0, 5);
1868 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1871 tmp = fieldFromInstruction(insn, 14, 5);
1872 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1873 tmp = fieldFromInstruction(insn, 0, 13);
1874 if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1877 tmp = fieldFromInstruction(insn, 25, 5);
1878 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1879 tmp = fieldFromInstruction(insn, 14, 5);
1880 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1881 tmp = fieldFromInstruction(insn, 0, 5);
1882 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1885 tmp = fieldFromInstruction(insn, 25, 5);
1886 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1887 tmp = fieldFromInstruction(insn, 14, 5);
1888 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1889 tmp = fieldFromInstruction(insn, 0, 6);
1890 MI.addOperand(MCOperand::createImm(tmp));
1893 tmp = fieldFromInstruction(insn, 25, 5);
1894 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1895 tmp = fieldFromInstruction(insn, 14, 5);
1896 if (DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1899 tmp = fieldFromInstruction(insn, 0, 13);
1900 MI.addOperand(MCOperand::createImm(tmp));
1903 tmp = fieldFromInstruction(insn, 25, 5);
1904 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1907 tmp = fieldFromInstruction(insn, 25, 5);
1908 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1909 tmp = fieldFromInstruction(insn, 14, 5);
1910 if (DecodePRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1913 tmp = fieldFromInstruction(insn, 25, 5);
1914 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1915 tmp = fieldFromInstruction(insn, 0, 5);
1916 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1917 tmp = fieldFromInstruction(insn, 25, 5);
1918 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1919 tmp = fieldFromInstruction(insn, 14, 4);
1920 MI.addOperand(MCOperand::createImm(tmp));
1923 tmp = fieldFromInstruction(insn, 25, 5);
1924 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1925 tmp = fieldFromInstruction(insn, 11, 2);
1926 if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1927 tmp = fieldFromInstruction(insn, 0, 5);
1928 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1929 tmp = fieldFromInstruction(insn, 25, 5);
1930 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1931 tmp = fieldFromInstruction(insn, 14, 4);
1932 MI.addOperand(MCOperand::createImm(tmp));
1935 tmp = fieldFromInstruction(insn, 25, 5);
1936 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1937 tmp = fieldFromInstruction(insn, 0, 11);
1938 MI.addOperand(MCOperand::createImm(tmp));
1939 tmp = fieldFromInstruction(insn, 25, 5);
1940 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1941 tmp = fieldFromInstruction(insn, 14, 4);
1942 MI.addOperand(MCOperand::createImm(tmp));
1945 tmp = fieldFromInstruction(insn, 25, 5);
1946 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1947 tmp = fieldFromInstruction(insn, 11, 2);
1948 if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1949 tmp = fieldFromInstruction(insn, 0, 11);
1950 MI.addOperand(MCOperand::createImm(tmp));
1951 tmp = fieldFromInstruction(insn, 25, 5);
1952 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1953 tmp = fieldFromInstruction(insn, 14, 4);
1954 MI.addOperand(MCOperand::createImm(tmp));
1957 tmp = fieldFromInstruction(insn, 25, 5);
1958 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1959 tmp = fieldFromInstruction(insn, 0, 5);
1960 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1963 tmp = fieldFromInstruction(insn, 25, 5);
1964 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1965 tmp = fieldFromInstruction(insn, 14, 5);
1966 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1967 tmp = fieldFromInstruction(insn, 0, 10);
1968 MI.addOperand(MCOperand::createImm(tmp));
1971 tmp = fieldFromInstruction(insn, 25, 5);
1972 if (DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1973 tmp = fieldFromInstruction(insn, 14, 5);
1974 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1975 tmp = fieldFromInstruction(insn, 0, 5);
1976 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1979 tmp = fieldFromInstruction(insn, 25, 5);
1980 if (DecodeASRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1981 tmp = fieldFromInstruction(insn, 14, 5);
1982 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1983 tmp = fieldFromInstruction(insn, 0, 13);
1984 if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1987 tmp = fieldFromInstruction(insn, 25, 5);
1988 if (DecodePRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1989 tmp = fieldFromInstruction(insn, 14, 5);
1990 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1991 tmp = fieldFromInstruction(insn, 0, 5);
1992 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1995 tmp = fieldFromInstruction(insn, 25, 5);
1996 if (DecodePRRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1997 tmp = fieldFromInstruction(insn, 14, 5);
1998 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
1999 tmp = fieldFromInstruction(insn, 0, 13);
2000 if (DecodeSIMM13(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2003 tmp = fieldFromInstruction(insn, 25, 5);
2004 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2005 tmp = fieldFromInstruction(insn, 0, 5);
2006 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2009 tmp = fieldFromInstruction(insn, 25, 5);
2010 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2011 tmp = fieldFromInstruction(insn, 0, 5);
2012 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2015 tmp = fieldFromInstruction(insn, 25, 5);
2016 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2017 tmp = fieldFromInstruction(insn, 0, 5);
2018 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2021 tmp = fieldFromInstruction(insn, 25, 5);
2022 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2023 tmp = fieldFromInstruction(insn, 14, 5);
2024 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2025 tmp = fieldFromInstruction(insn, 0, 5);
2026 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2029 tmp = fieldFromInstruction(insn, 25, 5);
2030 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2031 tmp = fieldFromInstruction(insn, 14, 5);
2032 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2033 tmp = fieldFromInstruction(insn, 0, 5);
2034 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2037 tmp = fieldFromInstruction(insn, 25, 5);
2038 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2039 tmp = fieldFromInstruction(insn, 14, 5);
2040 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2041 tmp = fieldFromInstruction(insn, 0, 5);
2042 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2045 tmp = fieldFromInstruction(insn, 25, 5);
2046 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2047 tmp = fieldFromInstruction(insn, 14, 5);
2048 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2049 tmp = fieldFromInstruction(insn, 0, 5);
2050 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2053 tmp = fieldFromInstruction(insn, 25, 5);
2054 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2055 tmp = fieldFromInstruction(insn, 14, 5);
2056 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2057 tmp = fieldFromInstruction(insn, 0, 5);
2058 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2061 tmp = fieldFromInstruction(insn, 25, 5);
2062 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2063 tmp = fieldFromInstruction(insn, 0, 5);
2064 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2067 tmp = fieldFromInstruction(insn, 25, 5);
2068 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2069 tmp = fieldFromInstruction(insn, 0, 5);
2070 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2073 tmp = fieldFromInstruction(insn, 25, 5);
2074 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2075 tmp = fieldFromInstruction(insn, 0, 5);
2076 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2079 tmp = fieldFromInstruction(insn, 25, 5);
2080 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2081 tmp = fieldFromInstruction(insn, 0, 5);
2082 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2085 tmp = fieldFromInstruction(insn, 25, 5);
2086 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2087 tmp = fieldFromInstruction(insn, 0, 5);
2088 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2091 tmp = fieldFromInstruction(insn, 25, 5);
2092 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2093 tmp = fieldFromInstruction(insn, 0, 5);
2094 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2097 tmp = fieldFromInstruction(insn, 25, 5);
2098 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2099 tmp = fieldFromInstruction(insn, 0, 5);
2100 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2101 tmp = fieldFromInstruction(insn, 25, 5);
2102 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2103 tmp = fieldFromInstruction(insn, 14, 4);
2104 MI.addOperand(MCOperand::createImm(tmp));
2107 tmp = fieldFromInstruction(insn, 25, 5);
2108 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2109 tmp = fieldFromInstruction(insn, 11, 2);
2110 if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2111 tmp = fieldFromInstruction(insn, 0, 5);
2112 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2113 tmp = fieldFromInstruction(insn, 25, 5);
2114 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2115 tmp = fieldFromInstruction(insn, 14, 4);
2116 MI.addOperand(MCOperand::createImm(tmp));
2119 tmp = fieldFromInstruction(insn, 25, 5);
2120 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2121 tmp = fieldFromInstruction(insn, 0, 5);
2122 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2123 tmp = fieldFromInstruction(insn, 25, 5);
2124 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2125 tmp = fieldFromInstruction(insn, 14, 4);
2126 MI.addOperand(MCOperand::createImm(tmp));
2129 tmp = fieldFromInstruction(insn, 25, 5);
2130 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2131 tmp = fieldFromInstruction(insn, 11, 2);
2132 if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2133 tmp = fieldFromInstruction(insn, 0, 5);
2134 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2135 tmp = fieldFromInstruction(insn, 25, 5);
2136 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2137 tmp = fieldFromInstruction(insn, 14, 4);
2138 MI.addOperand(MCOperand::createImm(tmp));
2141 tmp = fieldFromInstruction(insn, 25, 5);
2142 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2143 tmp = fieldFromInstruction(insn, 0, 5);
2144 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2145 tmp = fieldFromInstruction(insn, 25, 5);
2146 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2147 tmp = fieldFromInstruction(insn, 14, 4);
2148 MI.addOperand(MCOperand::createImm(tmp));
2151 tmp = fieldFromInstruction(insn, 25, 5);
2152 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2153 tmp = fieldFromInstruction(insn, 11, 2);
2154 if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2155 tmp = fieldFromInstruction(insn, 0, 5);
2156 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2157 tmp = fieldFromInstruction(insn, 25, 5);
2158 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2159 tmp = fieldFromInstruction(insn, 14, 4);
2160 MI.addOperand(MCOperand::createImm(tmp));
2163 tmp = fieldFromInstruction(insn, 25, 5);
2164 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2165 tmp = fieldFromInstruction(insn, 14, 5);
2166 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2167 tmp = fieldFromInstruction(insn, 0, 5);
2168 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2171 tmp = fieldFromInstruction(insn, 25, 5);
2172 if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2173 tmp = fieldFromInstruction(insn, 14, 5);
2174 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2175 tmp = fieldFromInstruction(insn, 0, 5);
2176 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2179 tmp = fieldFromInstruction(insn, 25, 5);
2180 if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2181 tmp = fieldFromInstruction(insn, 14, 5);
2182 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2183 tmp = fieldFromInstruction(insn, 0, 5);
2184 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2187 tmp = fieldFromInstruction(insn, 25, 5);
2188 if (DecodeFCCRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2189 tmp = fieldFromInstruction(insn, 14, 5);
2190 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2191 tmp = fieldFromInstruction(insn, 0, 5);
2192 if (DecodeQFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2195 tmp = fieldFromInstruction(insn, 25, 5);
2196 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2197 tmp = fieldFromInstruction(insn, 0, 5);
2198 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2201 tmp = fieldFromInstruction(insn, 0, 5);
2202 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2205 tmp = fieldFromInstruction(insn, 25, 5);
2206 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2207 tmp = fieldFromInstruction(insn, 14, 5);
2208 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2209 tmp = fieldFromInstruction(insn, 0, 5);
2210 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2213 tmp = fieldFromInstruction(insn, 25, 5);
2214 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2215 tmp = fieldFromInstruction(insn, 25, 5);
2216 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2219 tmp = fieldFromInstruction(insn, 25, 5);
2220 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2221 tmp = fieldFromInstruction(insn, 25, 5);
2222 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2225 tmp = fieldFromInstruction(insn, 25, 5);
2226 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2227 tmp = fieldFromInstruction(insn, 14, 5);
2228 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2231 tmp = fieldFromInstruction(insn, 25, 5);
2232 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2233 tmp = fieldFromInstruction(insn, 14, 5);
2234 if (DecodeFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2237 tmp = fieldFromInstruction(insn, 25, 5);
2238 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2239 tmp = fieldFromInstruction(insn, 0, 5);
2240 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2243 tmp = fieldFromInstruction(insn, 25, 5);
2244 if (DecodeDFPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2245 tmp = fieldFromInstruction(insn, 0, 5);
2246 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2255 tmp = fieldFromInstruction(insn, 14, 5);
2256 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2257 tmp = fieldFromInstruction(insn, 0, 5);
2258 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2259 tmp = fieldFromInstruction(insn, 25, 4);
2260 MI.addOperand(MCOperand::createImm(tmp));
2263 tmp = fieldFromInstruction(insn, 14, 5);
2264 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2265 tmp = fieldFromInstruction(insn, 0, 8);
2266 MI.addOperand(MCOperand::createImm(tmp));
2267 tmp = fieldFromInstruction(insn, 25, 4);
2268 MI.addOperand(MCOperand::createImm(tmp));
2286 tmp = fieldFromInstruction(insn, 5, 8);
2287 MI.addOperand(MCOperand::createImm(tmp));
2320 tmp = fieldFromInstruction(insn, 25, 5);
2321 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2322 tmp = fieldFromInstruction(insn, 14, 5);
2323 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2324 tmp = fieldFromInstruction(insn, 0, 5);
2325 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2326 tmp = fieldFromInstruction(insn, 25, 5);
2327 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2330 tmp = fieldFromInstruction(insn, 25, 5);
2331 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2332 tmp = fieldFromInstruction(insn, 14, 5);
2333 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2334 tmp = fieldFromInstruction(insn, 0, 5);
2335 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2336 tmp = fieldFromInstruction(insn, 25, 5);
2337 if (DecodeIntRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2338 tmp = fieldFromInstruction(insn, 5, 8);
2339 MI.addOperand(MCOperand::createImm(tmp));
2342 tmp = fieldFromInstruction(insn, 25, 5);
2343 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2344 tmp = fieldFromInstruction(insn, 14, 5);
2345 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2346 tmp = fieldFromInstruction(insn, 0, 5);
2347 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
2348 tmp = fieldFromInstruction(insn, 25, 5);
2349 if (DecodeI64RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }