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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 188 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
433 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
468 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
501 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
536 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
616 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
661 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
725 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
842 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
gen/lib/Target/RISCV/RISCVGenInstrInfo.inc 614 static const MCOperandInfo OperandInfo64[] = { { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
614 static const MCOperandInfo OperandInfo64[] = { { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
615 static const MCOperandInfo OperandInfo65[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
622 static const MCOperandInfo OperandInfo72[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
624 static const MCOperandInfo OperandInfo74[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
627 static const MCOperandInfo OperandInfo77[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
633 static const MCOperandInfo OperandInfo83[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
gen/lib/Target/RISCV/RISCVGenRegisterBank.inc 43 (1u << (RISCV::SPRegClassID - 0)) |
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 615 { SP, SPBits, 70, 1, sizeof(SPBits), RISCV::SPRegClassID, 1, true },
1449 &RISCVMCRegisterClasses[SPRegClassID],