reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc
  133       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
  134       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) {
  145       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
  146       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
  157       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
  158       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) {
  171       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg())) &&
  172       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
  211       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
  225       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
  252       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
  253       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
  268       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
  283       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
  577       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
  588       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
  615       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
  660       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
  742       (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
gen/lib/Target/RISCV/RISCVGenInstrInfo.inc
  612 static const MCOperandInfo OperandInfo62[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
  612 static const MCOperandInfo OperandInfo62[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
  612 static const MCOperandInfo OperandInfo62[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
  613 static const MCOperandInfo OperandInfo63[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
  613 static const MCOperandInfo OperandInfo63[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
  618 static const MCOperandInfo OperandInfo68[] = { { RISCV::GPRX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
  625 static const MCOperandInfo OperandInfo75[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
  627 static const MCOperandInfo OperandInfo77[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
  628 static const MCOperandInfo OperandInfo78[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
  631 static const MCOperandInfo OperandInfo81[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
  631 static const MCOperandInfo OperandInfo81[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
  632 static const MCOperandInfo OperandInfo82[] = { { RISCV::GPRX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
gen/lib/Target/RISCV/RISCVGenRegisterBank.inc
   38     (1u << (RISCV::GPRNoX0RegClassID - 0)) |
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc
  608   { GPRNoX0, GPRNoX0Bits, 6, 31, sizeof(GPRNoX0Bits), RISCV::GPRNoX0RegClassID, 1, true },
 1365     &RISCVMCRegisterClasses[GPRNoX0RegClassID],