reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
187 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 299 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 300 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 314 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 315 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 331 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 332 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 345 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 346 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 362 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 379 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 394 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 418 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 452 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 486 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 520 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 600 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 601 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 646 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 647 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 678 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 679 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 692 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 693 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 709 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 710 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 759 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 776 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 793 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 794 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 811 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 812 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 827 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 828 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 867 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 868 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 881 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 882 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) {gen/lib/Target/RISCV/RISCVGenInstrInfo.inc
615 static const MCOperandInfo OperandInfo65[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 617 static const MCOperandInfo OperandInfo67[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 617 static const MCOperandInfo OperandInfo67[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 617 static const MCOperandInfo OperandInfo67[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 619 static const MCOperandInfo OperandInfo69[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 619 static const MCOperandInfo OperandInfo69[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 620 static const MCOperandInfo OperandInfo70[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 621 static const MCOperandInfo OperandInfo71[] = { { RISCV::FPR64CRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 623 static const MCOperandInfo OperandInfo73[] = { { RISCV::FPR32CRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 626 static const MCOperandInfo OperandInfo76[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 626 static const MCOperandInfo OperandInfo76[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 635 static const MCOperandInfo OperandInfo85[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 635 static const MCOperandInfo OperandInfo85[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };gen/lib/Target/RISCV/RISCVGenRegisterBank.inc
42 (1u << (RISCV::GPRCRegClassID - 0)) |
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc612 { GPRC, GPRCBits, 50, 8, sizeof(GPRCBits), RISCV::GPRCRegClassID, 1, true }, 1413 &RISCVMCRegisterClasses[GPRCRegClassID],