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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2302 { 2212 /* neg */, RISCV::SUB, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
2372 { 2516 /* sub */, RISCV::SUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc 2724 case RISCV::SUB:
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 790 case RISCV::SUB: {
1686 OutInst.setOpcode(RISCV::SUB);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc11525 /* 21324*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11535 /* 21347*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11548 /* 21375*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11558 /* 21398*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11571 /* 21426*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11581 /* 21449*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11594 /* 21477*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11604 /* 21500*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11617 /* 21528*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11627 /* 21551*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11643 /* 21585*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11653 /* 21608*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11666 /* 21636*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11676 /* 21659*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11689 /* 21687*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11699 /* 21710*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11712 /* 21738*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11722 /* 21761*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11735 /* 21789*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11745 /* 21812*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11764 /* 21852*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11775 /* 21877*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11786 /* 21902*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11797 /* 21927*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11808 /* 21952*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11822 /* 21983*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11833 /* 22008*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11844 /* 22033*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11855 /* 22058*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11866 /* 22083*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
11914 /* 22162*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SUB), 0,
11919 /* 22171*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SUB), 0,
11926 /* 22184*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SUB), 0,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 453 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB,
460 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB,
476 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB,
5240 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5266 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5292 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5318 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5344 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5370 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5396 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5448 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5474 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5500 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5526 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5552 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5578 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5604 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5630 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5656 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5682 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5708 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5734 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5766 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5792 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5818 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5844 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5870 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5896 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5922 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5948 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
5974 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
6000 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 1255 case RISCV::SUB:
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 332 BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg)
lib/Target/RISCV/RISCVFrameLowering.cpp 83 Opc = RISCV::SUB;