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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2340 { 2408 /* sgtu */, RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
2355 { 2456 /* sltu */, RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
2358 { 2466 /* snez */, RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc 2712 case RISCV::SLTU:
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 6706 /* 12364*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6712 /* 12376*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6788 /* 12531*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6797 /* 12553*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6823 /* 12599*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6828 /* 12608*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6838 /* 12626*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6843 /* 12635*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6892 /* 12740*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6900 /* 12760*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
6910 /* 12778*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
6918 /* 12798*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
6931 /* 12827*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
6939 /* 12847*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
7008 /* 13002*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
7055 /* 13100*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
7072 /* 13131*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
7080 /* 13146*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
7110 /* 13213*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
7118 /* 13228*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
7129 /* 13254*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc10105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10278 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10463 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10494 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10515 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10536 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10557 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10806 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10893 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
10909 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
10930 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 1250 case RISCV::SLTU: