|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2334 { 2381 /* seqz */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__imm_95_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
2354 { 2450 /* sltiu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
2356 { 2456 /* sltu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc 2699 case RISCV::SLTIU:
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 6690 /* 12333*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
6696 /* 12345*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
6747 /* 12440*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
6753 /* 12451*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
6766 /* 12480*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
6775 /* 12502*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
6871 /* 12691*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
6879 /* 12711*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7000 /* 12986*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7033 /* 13048*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7044 /* 13074*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7099 /* 13187*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7348 /* 13719*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7361 /* 13757*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7375 /* 13797*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7569 /* 14199*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7582 /* 14237*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
7596 /* 14277*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc10075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10226 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10699 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
10857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11101 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
11412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 773 case RISCV::SLTIU: