|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenInstrInfo.inc 886 { 224, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #224 = ADD
889 { 227, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #227 = ADDW
890 { 228, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #228 = AMOADD_D
891 { 229, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #229 = AMOADD_D_AQ
892 { 230, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #230 = AMOADD_D_AQ_RL
893 { 231, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #231 = AMOADD_D_RL
894 { 232, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #232 = AMOADD_W
895 { 233, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #233 = AMOADD_W_AQ
896 { 234, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #234 = AMOADD_W_AQ_RL
897 { 235, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #235 = AMOADD_W_RL
898 { 236, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #236 = AMOAND_D
899 { 237, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #237 = AMOAND_D_AQ
900 { 238, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #238 = AMOAND_D_AQ_RL
901 { 239, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #239 = AMOAND_D_RL
902 { 240, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #240 = AMOAND_W
903 { 241, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #241 = AMOAND_W_AQ
904 { 242, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #242 = AMOAND_W_AQ_RL
905 { 243, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #243 = AMOAND_W_RL
906 { 244, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #244 = AMOMAXU_D
907 { 245, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #245 = AMOMAXU_D_AQ
908 { 246, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #246 = AMOMAXU_D_AQ_RL
909 { 247, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #247 = AMOMAXU_D_RL
910 { 248, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #248 = AMOMAXU_W
911 { 249, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #249 = AMOMAXU_W_AQ
912 { 250, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #250 = AMOMAXU_W_AQ_RL
913 { 251, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #251 = AMOMAXU_W_RL
914 { 252, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #252 = AMOMAX_D
915 { 253, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #253 = AMOMAX_D_AQ
916 { 254, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #254 = AMOMAX_D_AQ_RL
917 { 255, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #255 = AMOMAX_D_RL
918 { 256, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #256 = AMOMAX_W
919 { 257, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #257 = AMOMAX_W_AQ
920 { 258, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #258 = AMOMAX_W_AQ_RL
921 { 259, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #259 = AMOMAX_W_RL
922 { 260, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #260 = AMOMINU_D
923 { 261, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #261 = AMOMINU_D_AQ
924 { 262, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #262 = AMOMINU_D_AQ_RL
925 { 263, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #263 = AMOMINU_D_RL
926 { 264, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #264 = AMOMINU_W
927 { 265, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #265 = AMOMINU_W_AQ
928 { 266, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #266 = AMOMINU_W_AQ_RL
929 { 267, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #267 = AMOMINU_W_RL
930 { 268, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #268 = AMOMIN_D
931 { 269, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #269 = AMOMIN_D_AQ
932 { 270, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #270 = AMOMIN_D_AQ_RL
933 { 271, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #271 = AMOMIN_D_RL
934 { 272, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #272 = AMOMIN_W
935 { 273, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #273 = AMOMIN_W_AQ
936 { 274, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #274 = AMOMIN_W_AQ_RL
937 { 275, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #275 = AMOMIN_W_RL
938 { 276, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #276 = AMOOR_D
939 { 277, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #277 = AMOOR_D_AQ
940 { 278, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #278 = AMOOR_D_AQ_RL
941 { 279, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #279 = AMOOR_D_RL
942 { 280, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #280 = AMOOR_W
943 { 281, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #281 = AMOOR_W_AQ
944 { 282, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #282 = AMOOR_W_AQ_RL
945 { 283, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #283 = AMOOR_W_RL
946 { 284, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #284 = AMOSWAP_D
947 { 285, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #285 = AMOSWAP_D_AQ
948 { 286, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #286 = AMOSWAP_D_AQ_RL
949 { 287, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #287 = AMOSWAP_D_RL
950 { 288, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #288 = AMOSWAP_W
951 { 289, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #289 = AMOSWAP_W_AQ
952 { 290, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #290 = AMOSWAP_W_AQ_RL
953 { 291, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #291 = AMOSWAP_W_RL
954 { 292, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #292 = AMOXOR_D
955 { 293, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #293 = AMOXOR_D_AQ
956 { 294, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #294 = AMOXOR_D_AQ_RL
957 { 295, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #295 = AMOXOR_D_RL
958 { 296, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #296 = AMOXOR_W
959 { 297, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #297 = AMOXOR_W_AQ
960 { 298, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #298 = AMOXOR_W_AQ_RL
961 { 299, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #299 = AMOXOR_W_RL
962 { 300, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #300 = AND
1032 { 370, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #370 = DIV
1033 { 371, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #371 = DIVU
1034 { 372, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #372 = DIVUW
1035 { 373, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #373 = DIVW
1122 { 460, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #460 = MUL
1123 { 461, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #461 = MULH
1124 { 462, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #462 = MULHSU
1125 { 463, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #463 = MULHU
1126 { 464, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #464 = MULW
1127 { 465, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #465 = OR
1129 { 467, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #467 = REM
1130 { 468, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #468 = REMU
1131 { 469, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #469 = REMUW
1132 { 470, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #470 = REMW
1134 { 472, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #472 = SC_D
1135 { 473, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #473 = SC_D_AQ
1136 { 474, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #474 = SC_D_AQ_RL
1137 { 475, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #475 = SC_D_RL
1138 { 476, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #476 = SC_W
1139 { 477, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #477 = SC_W_AQ
1140 { 478, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #478 = SC_W_AQ_RL
1141 { 479, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #479 = SC_W_RL
1145 { 483, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #483 = SLL
1148 { 486, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #486 = SLLW
1149 { 487, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #487 = SLT
1152 { 490, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #490 = SLTU
1153 { 491, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #491 = SRA
1156 { 494, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #494 = SRAW
1158 { 496, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #496 = SRL
1161 { 499, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #499 = SRLW
1162 { 500, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #500 = SUB
1163 { 501, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #501 = SUBW
1168 { 506, 3, 1, 4, 0, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #506 = XOR