reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References

gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc

 2293   { 2173 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
 2294   { 2173 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },

gen/lib/Target/RISCV/RISCVGenDAGISel.inc

  869 /*  1543*/              OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
  878 /*  1560*/              OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 1015 /*  1819*/            OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 1242 /*  2242*/              OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 1251 /*  2259*/              OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 1458 /*  2621*/              OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 1466 /*  2635*/              OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 1601 /*  2888*/            OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 1711 /*  3086*/            OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 2030 /*  3720*/            OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 2039 /*  3738*/            OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 2049 /*  3758*/          OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 2270 /*  4171*/            OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 2278 /*  4186*/            OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
 2402 /*  4419*/          OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,

gen/lib/Target/RISCV/RISCVGenGlobalISel.inc

 3428       GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
 3458       GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
 3549       GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
 3568       GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
 3658       GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
 3713       GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,

gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc

  770     case RISCV::LWU:

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 1801     emitLoadStoreSymbol(Inst, RISCV::LWU, IDLoc, Out, /*HasTmpReg=*/false);

lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  225     case RISCV::LWU:

lib/Target/RISCV/RISCVInstrInfo.cpp

   47   case RISCV::LWU:

lib/Target/RISCV/RISCVMergeBaseOffset.cpp

  217   case RISCV::LWU: