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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2276 { 2093 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
2277 { 2093 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 803 /* 1421*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
811 /* 1436*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
981 /* 1755*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
1176 /* 2120*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
1184 /* 2135*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
1398 /* 2517*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
1405 /* 2529*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
1567 /* 2824*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
1680 /* 3031*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
1931 /* 3523*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
1939 /* 3539*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
1949 /* 3559*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
2210 /* 4061*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
2217 /* 4074*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
2371 /* 4361*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 3369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3530 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
3694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 768 case RISCV::LHU:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 1795 emitLoadStoreSymbol(Inst, RISCV::LHU, IDLoc, Out, /*HasTmpReg=*/false);
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 224 case RISCV::LHU:
lib/Target/RISCV/RISCVInstrInfo.cpp 44 case RISCV::LHU:
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 216 case RISCV::LHU: