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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2270 { 2087 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
2271 { 2087 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 597 case RISCV::LD: {
1397 OutInst.setOpcode(RISCV::LD);
1415 OutInst.setOpcode(RISCV::LD);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 890 /* 1582*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
899 /* 1599*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
1025 /* 1838*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
1263 /* 2281*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
1272 /* 2298*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
1477 /* 2654*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
1485 /* 2668*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
1611 /* 2907*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
1720 /* 3102*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
2062 /* 3784*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
2071 /* 3802*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
2081 /* 3822*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
2289 /* 4206*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
2297 /* 4221*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
2411 /* 4436*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
4699 /* 8693*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
4708 /* 8710*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
4753 /* 8794*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
4839 /* 8955*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
4848 /* 8972*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
4916 /* 9090*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
4924 /* 9104*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
4969 /* 9189*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
5005 /* 9253*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
5118 /* 9477*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
5127 /* 9495*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
5137 /* 9515*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
5208 /* 9647*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
5216 /* 9662*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
5257 /* 9738*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 1420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1975 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
1994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2070 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2425 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2682 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
2720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 766 case RISCV::LD:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 1674 SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
1693 unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
1804 emitLoadStoreSymbol(Inst, RISCV::LD, IDLoc, Out, /*HasTmpReg=*/false);
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 681 SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
696 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 226 case RISCV::LD:
lib/Target/RISCV/RISCVInstrInfo.cpp 48 case RISCV::LD:
150 RISCV::LW : RISCV::LD;
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 218 case RISCV::LD: