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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2267 { 2083 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
2268 { 2083 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 783 /* 1384*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
791 /* 1399*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
971 /* 1736*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
1156 /* 2083*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
1164 /* 2098*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
1380 /* 2486*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
1387 /* 2498*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
1557 /* 2805*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
1671 /* 3015*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
1900 /* 3461*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
1908 /* 3477*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
1918 /* 3497*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
2192 /* 4028*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
2199 /* 4041*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
2362 /* 4344*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 3311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3599 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
3676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 765 case RISCV::LBU:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 1789 emitLoadStoreSymbol(Inst, RISCV::LBU, IDLoc, Out, /*HasTmpReg=*/false);
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 223 case RISCV::LBU:
lib/Target/RISCV/RISCVInstrInfo.cpp 42 case RISCV::LBU:
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 215 case RISCV::LBU: