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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2246 { 2039 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
2247 { 2039 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 515 case RISCV::FSW: {
1301 OutInst.setOpcode(RISCV::FSW);
1320 OutInst.setOpcode(RISCV::FSW);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 3615 /* 6679*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3624 /* 6696*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3637 /* 6720*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3658 /* 6759*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3667 /* 6776*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3675 /* 6790*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3683 /* 6804*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3697 /* 6830*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3704 /* 6842*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3720 /* 6870*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3729 /* 6888*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3738 /* 6906*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3748 /* 6925*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3756 /* 6940*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
3766 /* 6958*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 3864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
3892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
3920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
4005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
4022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
4039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 737 case RISCV::FSW:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 1825 emitLoadStoreSymbol(Inst, RISCV::FSW, IDLoc, Out, /*HasTmpReg=*/true);
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 236 case RISCV::FSW:
lib/Target/RISCV/RISCVInstrInfo.cpp 70 case RISCV::FSW:
125 Opcode = RISCV::FSW;
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 225 case RISCV::FSW: