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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2219 { 1920 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
2220 { 1920 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 482 case RISCV::FSD: {
1264 OutInst.setOpcode(RISCV::FSD);
1282 OutInst.setOpcode(RISCV::FSD);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 3793 /* 7009*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3802 /* 7026*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3815 /* 7050*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3836 /* 7089*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3845 /* 7106*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3853 /* 7120*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3861 /* 7134*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3875 /* 7160*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3882 /* 7172*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3898 /* 7200*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3907 /* 7218*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3916 /* 7236*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3926 /* 7255*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3934 /* 7270*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
3944 /* 7288*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 4130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4158 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
4271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 736 case RISCV::FSD:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 1828 emitLoadStoreSymbol(Inst, RISCV::FSD, IDLoc, Out, /*HasTmpReg=*/true);
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 237 case RISCV::FSD:
lib/Target/RISCV/RISCVInstrInfo.cpp 72 case RISCV::FSD:
127 Opcode = RISCV::FSD;
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 226 case RISCV::FSD: {