|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2178 { 1718 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
2179 { 1718 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 447 case RISCV::FLW: {
1227 OutInst.setOpcode(RISCV::FLW);
1246 OutInst.setOpcode(RISCV::FLW);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 2437 /* 4486*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2446 /* 4503*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2481 /* 4569*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2513 /* 4632*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2522 /* 4649*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2530 /* 4663*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2538 /* 4677*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2590 /* 4773*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2597 /* 4785*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2633 /* 4851*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2642 /* 4869*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2651 /* 4887*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2661 /* 4906*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2669 /* 4921*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
2679 /* 4939*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 1600 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
1630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
1660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
2089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
2108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
2127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 762 case RISCV::FLW:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 1807 emitLoadStoreSymbol(Inst, RISCV::FLW, IDLoc, Out, /*HasTmpReg=*/true);
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 227 case RISCV::FLW:
lib/Target/RISCV/RISCVInstrInfo.cpp 46 case RISCV::FLW:
152 Opcode = RISCV::FLW;
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 219 case RISCV::FLW: