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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 2171 { 1690 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
2172 { 1690 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 414 case RISCV::FLD: {
1190 OutInst.setOpcode(RISCV::FLD);
1208 OutInst.setOpcode(RISCV::FLD);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 2457 /* 4524*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2466 /* 4541*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2490 /* 4587*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2549 /* 4698*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2558 /* 4715*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2566 /* 4729*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2574 /* 4743*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2608 /* 4806*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2615 /* 4818*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2690 /* 4961*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2699 /* 4979*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2708 /* 4997*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2718 /* 5016*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2726 /* 5031*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
2736 /* 5049*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 2455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2485 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2758 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
2777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 761 case RISCV::FLD:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 1810 emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true);
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 228 case RISCV::FLD:
lib/Target/RISCV/RISCVInstrInfo.cpp 49 case RISCV::FLD:
154 Opcode = RISCV::FLD;
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 220 case RISCV::FLD: