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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 1997 { 882 /* and */, RISCV::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 328 case RISCV::AND: {
1101 OutInst.setOpcode(RISCV::AND);
1115 OutInst.setOpcode(RISCV::AND);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 378 /* 624*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
383 /* 633*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
391 /* 647*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
7310 /* 13617*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
7320 /* 13644*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
7331 /* 13673*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
7345 /* 13708*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
7358 /* 13746*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
7372 /* 13786*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
7531 /* 14097*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
7541 /* 14124*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
7552 /* 14153*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
7566 /* 14188*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
7579 /* 14226*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
7593 /* 14266*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 804 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND,
812 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND,
865 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND,
11033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11096 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11133 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11200 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11232 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11269 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11339 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
11375 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
11407 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 1208 case RISCV::AND:
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 256 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
287 BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg)
337 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
458 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg)
588 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg)