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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 1919 { 0 /* add */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
1921 { 4 /* addi */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
2301 { 2209 /* mv */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
2304 { 2221 /* nop */, RISCV::ADDI, Convert__regX0__regX0__imm_95_0, AMFBS_None, { }, },
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc 1608 case RISCV::ADDI:
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 185 case RISCV::ADDI: {
999 OutInst.setOpcode(RISCV::ADDI);
1016 OutInst.setOpcode(RISCV::ADDI);
1033 OutInst.setOpcode(RISCV::ADDI);
1431 OutInst.setOpcode(RISCV::ADDI);
1536 OutInst.setOpcode(RISCV::ADDI);
1551 OutInst.setOpcode(RISCV::ADDI);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 5279 /* 9780*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
5286 /* 9794*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
5583 /* 10304*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
5590 /* 10318*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
5597 /* 10331*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
5603 /* 10342*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
5611 /* 10357*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
8332 /* 15525*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
8339 /* 15539*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
8348 /* 15557*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
8392 /* 15646*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
8404 /* 15674*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
8417 /* 15704*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 359 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
9512 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
9525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
9544 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 758 case RISCV::ADDI:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 1654 RISCV::ADDI, IDLoc, Out);
1677 SecondOpcode = RISCV::ADDI;
1709 RISCV::ADDI, IDLoc, Out);
1758 emitToStreamer(Out, MCInstBuilder(RISCV::ADDI)
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 461 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg)
669 RISCV::ADDI);
684 SecondOpcode = RISCV::ADDI;
705 RISCV::ADDI);
lib/Target/RISCV/RISCVFrameLowering.cpp 74 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
lib/Target/RISCV/RISCVISelDAGToDAG.cpp 133 ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
252 if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI)
lib/Target/RISCV/RISCVISelLowering.cpp 455 return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, AddrLo), 0);
541 return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNAdd, AddrLo), 0);
lib/Target/RISCV/RISCVInstrInfo.cpp 90 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
483 case RISCV::ADDI:
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 90 if (LoADDI->getOpcode() != RISCV::ADDI ||
147 if (OffsetTail.getOpcode() == RISCV::ADDI) {
190 case RISCV::ADDI: {
lib/Target/RISCV/Utils/RISCVMatInt.cpp 35 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
75 Res.push_back(Inst(RISCV::ADDI, Lo12));