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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 1341 case MCK_CSRSystemRegister: {
1707 case MCK_CSRSystemRegister: return "MCK_CSRSystemRegister";
2090 { 1290 /* csrc */, RISCV::CSRRC, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
2091 { 1290 /* csrc */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
2092 { 1295 /* csrci */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
2093 { 1301 /* csrr */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, },
2094 { 1306 /* csrrc */, RISCV::CSRRC, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
2095 { 1306 /* csrrc */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
2096 { 1312 /* csrrci */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
2097 { 1319 /* csrrs */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
2098 { 1319 /* csrrs */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
2099 { 1325 /* csrrsi */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
2100 { 1332 /* csrrw */, RISCV::CSRRW, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
2101 { 1332 /* csrrw */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
2102 { 1338 /* csrrwi */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
2103 { 1345 /* csrs */, RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
2104 { 1345 /* csrs */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
2105 { 1350 /* csrsi */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
2106 { 1356 /* csrw */, RISCV::CSRRW, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
2107 { 1356 /* csrw */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
2108 { 1361 /* csrwi */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
2692 { 1290 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
2693 { 1290 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
2694 { 1295 /* csrci */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
2695 { 1301 /* csrr */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2696 { 1306 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2697 { 1306 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2698 { 1312 /* csrrci */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2699 { 1319 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2700 { 1319 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2701 { 1325 /* csrrsi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2702 { 1332 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2703 { 1332 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2704 { 1338 /* csrrwi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
2705 { 1345 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
2706 { 1345 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
2707 { 1350 /* csrsi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
2708 { 1356 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
2709 { 1356 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
2710 { 1361 /* csrwi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
2761 case MCK_CSRSystemRegister: